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/*
    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
                 2011,2012,2013 Giovanni Di Sirio.

    This file is part of ChibiOS/RT.

    ChibiOS/RT is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3 of the License, or
    (at your option) any later version.

    ChibiOS/RT is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program.  If not, see <http://www.gnu.org/licenses/>.
*/

#define STM32F103_MCUCONF

/*
 * STM32F103 drivers configuration.
 * The following settings override the default settings present in
 * the various device driver implementation headers.
 * Note that the settings for each driver only have effect if the whole
 * driver is enabled in halconf.h.
 *
 * IRQ priorities:
 * 15...0       Lowest...Highest.
 *
 * DMA priorities:
 * 0...3        Lowest...Highest.
 */

/*
 * HAL driver system settings.
 */
#define STM32_NO_INIT                       FALSE
#define STM32_HSI_ENABLED                   TRUE
#define STM32_LSI_ENABLED                   FALSE
#define STM32_HSE_ENABLED                   TRUE
#define STM32_LSE_ENABLED                   FALSE
#define STM32_SW                            STM32_SW_PLL
#define STM32_PLLSRC                        STM32_PLLSRC_HSE
#define STM32_PLLXTPRE                      STM32_PLLXTPRE_DIV1
#define STM32_PLLMUL_VALUE                  9
#define STM32_HPRE                          STM32_HPRE_DIV1
#define STM32_PPRE1                         STM32_PPRE1_DIV2
#define STM32_PPRE2                         STM32_PPRE2_DIV2
#define STM32_ADCPRE                        STM32_ADCPRE_DIV4
#define STM32_USB_CLOCK_REQUIRED            TRUE
#define STM32_USBPRE                        STM32_USBPRE_DIV1P5
#define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK
#define STM32_RTCSEL                        STM32_RTCSEL_HSEDIV
#define STM32_PVD_ENABLE                    FALSE
#define STM32_PLS                           STM32_PLS_LEV0

/*
 * ADC driver system settings.
 */
#define STM32_ADC_USE_ADC1                  FALSE
#define STM32_ADC_ADC1_DMA_PRIORITY         2
#define STM32_ADC_ADC1_IRQ_PRIORITY         6

/*
 * CAN driver system settings.
 */
#define STM32_CAN_USE_CAN1                  FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY         11

/*
 * EXT driver system settings.
 */
#define STM32_EXT_EXTI0_IRQ_PRIORITY        6
#define STM32_EXT_EXTI1_IRQ_PRIORITY        6
#define STM32_EXT_EXTI2_IRQ_PRIORITY        6
#define STM32_EXT_EXTI3_IRQ_PRIORITY        6
#define STM32_EXT_EXTI4_IRQ_PRIORITY        6
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY      6
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY    6
#define STM32_EXT_EXTI16_IRQ_PRIORITY       6
#define STM32_EXT_EXTI17_IRQ_PRIORITY       6
#define STM32_EXT_EXTI18_IRQ_PRIORITY       6
#define STM32_EXT_EXTI19_IRQ_PRIORITY       6

/*
 * GPT driver system settings.
 */
#define STM32_GPT_USE_TIM1                  FALSE
#define STM32_GPT_USE_TIM2                  FALSE
#define STM32_GPT_USE_TIM3                  FALSE
#define STM32_GPT_USE_TIM4                  FALSE
#define STM32_GPT_USE_TIM5                  FALSE
#define STM32_GPT_USE_TIM8                  FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY         7
#define STM32_GPT_TIM2_IRQ_PRIORITY         7
#define STM32_GPT_TIM3_IRQ_PRIORITY         7
#define STM32_GPT_TIM4_IRQ_PRIORITY         7
#define STM32_GPT_TIM5_IRQ_PRIORITY         7
#define STM32_GPT_TIM8_IRQ_PRIORITY         7

/*
 * I2C driver system settings.
 */
#define STM32_I2C_USE_I2C1                  FALSE
#define STM32_I2C_USE_I2C2                  FALSE
#define STM32_I2C_I2C1_IRQ_PRIORITY         5
#define STM32_I2C_I2C2_IRQ_PRIORITY         5
#define STM32_I2C_I2C1_DMA_PRIORITY         3
#define STM32_I2C_I2C2_DMA_PRIORITY         3
#define STM32_I2C_I2C1_DMA_ERROR_HOOK()     chSysHalt()
#define STM32_I2C_I2C2_DMA_ERROR_HOOK()     chSysHalt()

/*
 * ICU driver system settings.
 */
#define STM32_ICU_USE_TIM1                  FALSE
#define STM32_ICU_USE_TIM2                  FALSE
#define STM32_ICU_USE_TIM3                  FALSE
#define STM32_ICU_USE_TIM4                  FALSE
#define STM32_ICU_USE_TIM5                  FALSE
#define STM32_ICU_USE_TIM8                  FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY         7
#define STM32_ICU_TIM2_IRQ_PRIORITY         7
#define STM32_ICU_TIM3_IRQ_PRIORITY         7
#define STM32_ICU_TIM4_IRQ_PRIORITY         7
#define STM32_ICU_TIM5_IRQ_PRIORITY         7
#define STM32_ICU_TIM8_IRQ_PRIORITY         7

/*
 * PWM driver system settings.
 */
#define STM32_PWM_USE_ADVANCED              FALSE
#define STM32_PWM_USE_TIM1                  FALSE
#define STM32_PWM_USE_TIM2                  FALSE
#define STM32_PWM_USE_TIM3                  FALSE
#define STM32_PWM_USE_TIM4                  FALSE
#define STM32_PWM_USE_TIM5                  FALSE
#define STM32_PWM_USE_TIM8                  FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY         7
#define STM32_PWM_TIM2_IRQ_PRIORITY         7
#define STM32_PWM_TIM3_IRQ_PRIORITY         7
#define STM32_PWM_TIM4_IRQ_PRIORITY         7
#define STM32_PWM_TIM5_IRQ_PRIORITY         7
#define STM32_PWM_TIM8_IRQ_PRIORITY         7

/*
 * RTC driver system settings.
 */
#define STM32_RTC_IRQ_PRIORITY              15

/*
 * SERIAL driver system settings.
 */
#define STM32_SERIAL_USE_USART1             FALSE
#define STM32_SERIAL_USE_USART2             TRUE
#define STM32_SERIAL_USE_USART3             FALSE
#define STM32_SERIAL_USE_UART4              FALSE
#define STM32_SERIAL_USE_UART5              FALSE
#define STM32_SERIAL_USART1_PRIORITY        12
#define STM32_SERIAL_USART2_PRIORITY        12
#define STM32_SERIAL_USART3_PRIORITY        12
#define STM32_SERIAL_UART4_PRIORITY         12
#define STM32_SERIAL_UART5_PRIORITY         12

/*
 * SPI driver system settings.
 */
#define STM32_SPI_USE_SPI1                  FALSE
#define STM32_SPI_USE_SPI2                  FALSE
#define STM32_SPI_USE_SPI3                  FALSE
#define STM32_SPI_SPI1_DMA_PRIORITY         1
#define STM32_SPI_SPI2_DMA_PRIORITY         1
#define STM32_SPI_SPI3_DMA_PRIORITY         1
#define STM32_SPI_SPI1_IRQ_PRIORITY         10
#define STM32_SPI_SPI2_IRQ_PRIORITY         10
#define STM32_SPI_SPI3_IRQ_PRIORITY         10
#define STM32_SPI_DMA_ERROR_HOOK(spip)      chSysHalt()

/*
 * UART driver system settings.
 */
#define STM32_UART_USE_USART1               FALSE
#define STM32_UART_USE_USART2               FALSE
#define STM32_UART_USE_USART3               FALSE
#define STM32_UART_USART1_IRQ_PRIORITY      12
#define STM32_UART_USART2_IRQ_PRIORITY      12
#define STM32_UART_USART3_IRQ_PRIORITY      12
#define STM32_UART_USART1_DMA_PRIORITY      0
#define STM32_UART_USART2_DMA_PRIORITY      0
#define STM32_UART_USART3_DMA_PRIORITY      0
#define STM32_UART_DMA_ERROR_HOOK(uartp)    chSysHalt()

/*
 * USB driver system settings.
 */
#define STM32_USB_USE_USB1                  FALSE
#define STM32_USB_LOW_POWER_ON_SUSPEND      FALSE
#define STM32_USB_USB1_HP_IRQ_PRIORITY      13
#define STM32_USB_USB1_LP_IRQ_PRIORITY      14
end the given 32-bit address to the target, LSB first */ XPROGTarget_SendByte(AbsoluteAddress & 0xFF); XPROGTarget_SendByte(AbsoluteAddress >> 8); XPROGTarget_SendByte(AbsoluteAddress >> 16); XPROGTarget_SendByte(AbsoluteAddress >> 24); } /** Sends the given NVM register address to the target. * * \param[in] Register NVM register whose absolute address is to be sent */ static void XMEGANVM_SendNVMRegAddress(const uint8_t Register) { /* Determine the absolute register address from the NVM base memory address and the NVM register address */ uint32_t Address = XPROG_Param_NVMBase | Register; /* Send the calculated 32-bit address to the target, LSB first */ XMEGANVM_SendAddress(Address); } /** Busy-waits while the NVM controller is busy performing a NVM operation, such as a FLASH page read or CRC * calculation. * * \return Boolean \c true if the NVM controller became ready within the timeout period, \c false otherwise */ bool XMEGANVM_WaitWhileNVMBusBusy(void) { /* Poll the STATUS register to check to see if NVM access has been enabled */ for (;;) { /* Send the LDCS command to read the PDI STATUS register to see the NVM bus is active */ XPROGTarget_SendByte(PDI_CMD_LDCS(PDI_REG_STATUS)); uint8_t StatusRegister = XPROGTarget_ReceiveByte(); /* We might have timed out waiting for the status register read response, check here */ if (!(TimeoutTicksRemaining)) return false; /* Check the status register read response to see if the NVM bus is enabled */ if (StatusRegister & PDI_STATUS_NVM) return true; } } /** Waits while the target's NVM controller is busy performing an operation, exiting if the * timeout period expires. * * \return Boolean \c true if the NVM controller became ready within the timeout period, \c false otherwise */ bool XMEGANVM_WaitWhileNVMControllerBusy(void) { /* Preload the pointer register with the NVM STATUS register address to check the BUSY flag */ XPROGTarget_SendByte(PDI_CMD_ST(PDI_POINTER_DIRECT, PDI_DATASIZE_4BYTES)); XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_STATUS); /* Poll the NVM STATUS register while the NVM controller is busy */ for (;;) { /* Fetch the current status value via the pointer register (without auto-increment afterwards) */ XPROGTarget_SendByte(PDI_CMD_LD(PDI_POINTER_INDIRECT, PDI_DATASIZE_1BYTE)); uint8_t StatusRegister = XPROGTarget_ReceiveByte(); /* We might have timed out waiting for the status register read response, check here */ if (!(TimeoutTicksRemaining)) return false; /* Check to see if the BUSY flag is still set */ if (!(StatusRegister & (1 << 7))) return true; } } /** Enables the physical PDI interface on the target and enables access to the internal NVM controller. * * \return Boolean \c true if the PDI interface was enabled successfully, \c false otherwise */ bool XMEGANVM_EnablePDI(void) { /* Enable PDI programming mode with the attached target */ XPROGTarget_EnableTargetPDI(); /* Store the RESET key into the RESET PDI register to keep the XMEGA in reset */ XPROGTarget_SendByte(PDI_CMD_STCS(PDI_REG_RESET)); XPROGTarget_SendByte(PDI_RESET_KEY); /* Lower direction change guard time to 32 USART bits */ XPROGTarget_SendByte(PDI_CMD_STCS(PDI_REG_CTRL)); XPROGTarget_SendByte(0x02); /* Enable access to the XPROG NVM bus by sending the documented NVM access key to the device */ XPROGTarget_SendByte(PDI_CMD_KEY); for (uint8_t i = sizeof(PDI_NVMENABLE_KEY); i > 0; i--) XPROGTarget_SendByte(PDI_NVMENABLE_KEY[i - 1]); /* Wait until the NVM bus becomes active */ return XMEGANVM_WaitWhileNVMBusBusy(); } /** Removes access to the target's NVM controller and physically disables the target's physical PDI interface. */ void XMEGANVM_DisablePDI(void) { XMEGANVM_WaitWhileNVMBusBusy(); /* Clear the RESET key in the RESET PDI register to allow the XMEGA to run - must perform this until the * change takes effect, as in some cases it takes multiple writes (silicon bug?). */ do { /* Clear reset register */ XPROGTarget_SendByte(PDI_CMD_STCS(PDI_REG_RESET)); XPROGTarget_SendByte(0x00); /* Read back the reset register, check to see if it took effect */ XPROGTarget_SendByte(PDI_CMD_LDCS(PDI_REG_RESET)); } while (XPROGTarget_ReceiveByte() != 0x00); XPROGTarget_DisableTargetPDI(); } /** Retrieves the CRC value of the given memory space. * * \param[in] CRCCommand NVM CRC command to issue to the target * \param[out] CRCDest CRC Destination when read from the target * * \return Boolean \c true if the command sequence complete successfully */ bool XMEGANVM_GetMemoryCRC(const uint8_t CRCCommand, uint32_t* const CRCDest) { *CRCDest = 0; /* Wait until the NVM controller is no longer busy */ if (!(XMEGANVM_WaitWhileNVMControllerBusy())) return false; /* Set the NVM command to the correct CRC read command */ XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE)); XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD); XPROGTarget_SendByte(CRCCommand); /* Set CMDEX bit in NVM CTRLA register to start the CRC generation */ XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE)); XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CTRLA); XPROGTarget_SendByte(XMEGA_NVM_BIT_CTRLA_CMDEX); /* Wait until the NVM bus is ready again */ if (!(XMEGANVM_WaitWhileNVMBusBusy())) return false; /* Wait until the NVM controller is no longer busy */ if (!(XMEGANVM_WaitWhileNVMControllerBusy())) return false; /* Load the PDI pointer register with the DAT0 register start address */ XPROGTarget_SendByte(PDI_CMD_ST(PDI_POINTER_DIRECT, PDI_DATASIZE_4BYTES)); XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_DAT0); /* Send the REPEAT command to grab the CRC bytes */ XPROGTarget_SendByte(PDI_CMD_REPEAT(PDI_DATASIZE_1BYTE)); XPROGTarget_SendByte(XMEGA_CRC_LENGTH_BYTES - 1); /* Read in the CRC bytes from the target */ XPROGTarget_SendByte(PDI_CMD_LD(PDI_POINTER_INDIRECT_PI, PDI_DATASIZE_1BYTE)); for (uint8_t i = 0; i < XMEGA_CRC_LENGTH_BYTES; i++) ((uint8_t*)CRCDest)[i] = XPROGTarget_ReceiveByte(); return (TimeoutTicksRemaining > 0); } /** Reads memory from the target's memory spaces. * * \param[in] ReadAddress Start address to read from within the target's address space * \param[out] ReadBuffer Buffer to store read data into * \param[in] ReadSize Number of bytes to read * * \return Boolean \c true if the command sequence complete successfully */ bool XMEGANVM_ReadMemory(const uint32_t ReadAddress, uint8_t* ReadBuffer, uint16_t ReadSize) { /* Wait until the NVM controller is no longer busy */ if (!(XMEGANVM_WaitWhileNVMControllerBusy())) return false; /* Send the READNVM command to the NVM controller for reading of an arbitrary location */ XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE)); XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD); XPROGTarget_SendByte(XMEGA_NVM_CMD_READNVM); if (ReadSize > 1) { /* Load the PDI pointer register with the start address we want to read from */ XPROGTarget_SendByte(PDI_CMD_ST(PDI_POINTER_DIRECT, PDI_DATASIZE_4BYTES)); XMEGANVM_SendAddress(ReadAddress); /* Send the REPEAT command with the specified number of bytes to read */ XPROGTarget_SendByte(PDI_CMD_REPEAT(PDI_DATASIZE_1BYTE)); XPROGTarget_SendByte(ReadSize - 1); /* Send a LD command with indirect access and post-increment to read out the bytes */ XPROGTarget_SendByte(PDI_CMD_LD(PDI_POINTER_INDIRECT_PI, PDI_DATASIZE_1BYTE)); while (ReadSize-- && TimeoutTicksRemaining) *(ReadBuffer++) = XPROGTarget_ReceiveByte(); } else { /* Send a LDS command with the read address to read out the requested byte */ XPROGTarget_SendByte(PDI_CMD_LDS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE)); XMEGANVM_SendAddress(ReadAddress); *(ReadBuffer++) = XPROGTarget_ReceiveByte(); } return (TimeoutTicksRemaining > 0); } /** Writes byte addressed memory to the target's memory spaces. * * \param[in] WriteCommand Command to send to the device to write each memory byte * \param[in] WriteAddress Address to write to within the target's address space * \param[in] Byte Byte to write to the target * * \return Boolean \c true if the command sequence complete successfully */ bool XMEGANVM_WriteByteMemory(const uint8_t WriteCommand, const uint32_t WriteAddress, const uint8_t Byte) { /* Wait until the NVM controller is no longer busy */ if (!(XMEGANVM_WaitWhileNVMControllerBusy())) return false; /* Send the memory write command to the target */ XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE)); XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD); XPROGTarget_SendByte(WriteCommand); /* Send new memory byte to the memory of the target */ XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE)); XMEGANVM_SendAddress(WriteAddress); XPROGTarget_SendByte(Byte); return true; } /** Writes page addressed memory to the target's memory spaces. * * \param[in] WriteBuffCommand Command to send to the device to write a byte to the memory page buffer * \param[in] EraseBuffCommand Command to send to the device to erase the memory page buffer * \param[in] WritePageCommand Command to send to the device to write the page buffer to the destination memory * \param[in] PageMode Bitfield indicating what operations need to be executed on the specified page * \param[in] WriteAddress Start address to write the page data to within the target's address space * \param[in] WriteBuffer Buffer to source data from * \param[in] WriteSize Number of bytes to write * * \return Boolean \c true if the command sequence complete successfully */ bool XMEGANVM_WritePageMemory(const uint8_t WriteBuffCommand, const uint8_t EraseBuffCommand, const uint8_t WritePageCommand, const uint8_t PageMode, const uint32_t WriteAddress, const uint8_t* WriteBuffer, uint16_t WriteSize) { if (PageMode & XPROG_PAGEMODE_ERASE) { /* Wait until the NVM controller is no longer busy */ if (!(XMEGANVM_WaitWhileNVMControllerBusy())) return false; /* Send the memory buffer erase command to the target */ XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE)); XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD); XPROGTarget_SendByte(EraseBuffCommand); /* Set CMDEX bit in NVM CTRLA register to start the buffer erase */ XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE)); XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CTRLA); XPROGTarget_SendByte(XMEGA_NVM_BIT_CTRLA_CMDEX); } if (WriteSize) { /* Wait until the NVM controller is no longer busy */ if (!(XMEGANVM_WaitWhileNVMControllerBusy())) return false; /* Send the memory buffer write command to the target */ XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE)); XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD); XPROGTarget_SendByte(WriteBuffCommand); /* Load the PDI pointer register with the start address we want to write to */ XPROGTarget_SendByte(PDI_CMD_ST(PDI_POINTER_DIRECT, PDI_DATASIZE_4BYTES)); XMEGANVM_SendAddress(WriteAddress); /* Send the REPEAT command with the specified number of bytes to write */ XPROGTarget_SendByte(PDI_CMD_REPEAT(PDI_DATASIZE_1BYTE)); XPROGTarget_SendByte(WriteSize - 1); /* Send a ST command with indirect access and post-increment to write the bytes */ XPROGTarget_SendByte(PDI_CMD_ST(PDI_POINTER_INDIRECT_PI, PDI_DATASIZE_1BYTE)); while (WriteSize--) XPROGTarget_SendByte(*(WriteBuffer++)); } if (PageMode & XPROG_PAGEMODE_WRITE) { /* Wait until the NVM controller is no longer busy */ if (!(XMEGANVM_WaitWhileNVMControllerBusy())) return false; /* Send the memory write command to the target */ XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE)); XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD); XPROGTarget_SendByte(WritePageCommand); /* Send the address of the first page location to write the memory page */ XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE)); XMEGANVM_SendAddress(WriteAddress); XPROGTarget_SendByte(0x00); } return true; } /** Erases a specific memory space of the target. * * \param[in] EraseCommand NVM erase command to send to the device * \param[in] Address Address inside the memory space to erase * * \return Boolean \c true if the command sequence complete successfully */ bool XMEGANVM_EraseMemory(const uint8_t EraseCommand, const uint32_t Address) { /* Wait until the NVM controller is no longer busy */ if (!(XMEGANVM_WaitWhileNVMControllerBusy())) return false; /* EEPROM and Chip erasures are triggered differently to FLASH section erasures */ if (EraseCommand == XMEGA_NVM_CMD_CHIPERASE) { /* Send the memory erase command to the target */ XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE)); XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD); XPROGTarget_SendByte(EraseCommand); /* Set CMDEX bit in NVM CTRLA register to start the erase sequence */ XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE)); XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CTRLA); XPROGTarget_SendByte(XMEGA_NVM_BIT_CTRLA_CMDEX); } else if (EraseCommand == XMEGA_NVM_CMD_ERASEEEPROM) { /* Send the EEPROM page buffer erase command to the target */ XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE)); XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD); XPROGTarget_SendByte(XMEGA_NVM_CMD_ERASEEEPROMPAGEBUFF); /* Set CMDEX bit in NVM CTRLA register to start the buffer erase */ XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE)); XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CTRLA); XPROGTarget_SendByte(XMEGA_NVM_BIT_CTRLA_CMDEX); /* Wait until the NVM controller is no longer busy */ if (!(XMEGANVM_WaitWhileNVMControllerBusy())) return false; /* Send the EEPROM memory buffer write command to the target */ XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE)); XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD); XPROGTarget_SendByte(XMEGA_NVM_CMD_LOADEEPROMPAGEBUFF); /* Load the PDI pointer register with the EEPROM page start address */ XPROGTarget_SendByte(PDI_CMD_ST(PDI_POINTER_DIRECT, PDI_DATASIZE_4BYTES)); XMEGANVM_SendAddress(Address); /* Send the REPEAT command with the specified number of bytes to write */ XPROGTarget_SendByte(PDI_CMD_REPEAT(PDI_DATASIZE_1BYTE)); XPROGTarget_SendByte(XPROG_Param_EEPageSize - 1); /* Send a ST command with indirect access and post-increment to tag each byte in the EEPROM page buffer */ XPROGTarget_SendByte(PDI_CMD_ST(PDI_POINTER_INDIRECT_PI, PDI_DATASIZE_1BYTE)); for (uint8_t PageByte = 0; PageByte < XPROG_Param_EEPageSize; PageByte++) XPROGTarget_SendByte(0x00); /* Send the memory erase command to the target */ XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE)); XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD); XPROGTarget_SendByte(EraseCommand); /* Set CMDEX bit in NVM CTRLA register to start the EEPROM erase sequence */ XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE)); XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CTRLA); XPROGTarget_SendByte(XMEGA_NVM_BIT_CTRLA_CMDEX); } else { /* Send the memory erase command to the target */ XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE)); XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD); XPROGTarget_SendByte(EraseCommand); /* Other erase modes just need us to address a byte within the target memory space */ XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE)); XMEGANVM_SendAddress(Address); XPROGTarget_SendByte(0x00); } /* Wait until the NVM bus is ready again */ if (!(XMEGANVM_WaitWhileNVMBusBusy())) return false; /* Wait until the NVM controller is no longer busy */ if (!(XMEGANVM_WaitWhileNVMControllerBusy())) return false; return true; } #endif