1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
|
/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
LPC17xx DMA driver - Copyright (C) 2013 Marcin Jokel
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file LPC17xx/LPC17xx_dma.h
* @brief DMA driver header.
*
* @addtogroup LPC17xx_DMA
* @{
*/
#ifndef _LPC17xx_DMA_H_
#define _LPC17xx_DMA_H_
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
#define DMACCONFIG_E (1UL << 0)
#define DMACCONFIG_M (1UL << 1)
/**
* @brief Total number of DMA streams.
* @note This is the total number of streams among all the DMA units.
*/
#define LPC17xx_DMA_CHANNELS 8
/**
* @name DMA control data configuration
* @{
*/
/**
* @brief DMA transfer size.
*
* @param[in] n DMA transfer size
*/
#define DMA_CTRL_TRANSFER_SIZE(n) (n)
/**
* @brief DMA source burst size.
*/
#define DMA_CTRL_SRC_BSIZE_1 (0 << 12)
#define DMA_CTRL_SRC_BSIZE_4 (1UL << 12)
#define DMA_CTRL_SRC_BSIZE_8 (2UL << 12)
#define DMA_CTRL_SRC_BSIZE_16 (3UL << 12)
#define DMA_CTRL_SRC_BSIZE_32 (4UL << 12)
#define DMA_CTRL_SRC_BSIZE_64 (5UL << 12)
#define DMA_CTRL_SRC_BSIZE_128 (6UL << 12)
#define DMA_CTRL_SRC_BSIZE_256 (7UL << 12)
/**
* @brief DMA destination burst size.
* @{
*/
#define DMA_CTRL_DST_BSIZE_1 (0 << 15)
#define DMA_CTRL_DST_BSIZE_4 (1UL << 15)
#define DMA_CTRL_DST_BSIZE_8 (2UL << 15)
#define DMA_CTRL_DST_BSIZE_16 (3UL << 15)
#define DMA_CTRL_DST_BSIZE_32 (4UL << 15)
#define DMA_CTRL_DST_BSIZE_64 (5UL << 15)
#define DMA_CTRL_DST_BSIZE_128 (6UL << 15)
#define DMA_CTRL_DST_BSIZE_256 (7UL << 15)
/** @} */
/**
* @name DMA source transfer width.
* @{
*/
#define DMA_CTRL_SRC_WIDTH_BYTE (0 << 18)
#define DMA_CTRL_SRC_WIDTH_HWORD (1UL << 18)
#define DMA_CTRL_SRC_WIDTH_WORD (2UL << 18)
/** @} */
/**
* @name DMA destination transfer width.
* @{
*/
#define DMA_CTRL_DST_WIDTH_BYTE (0 << 21)
#define DMA_CTRL_DST_WIDTH_HWORD (1UL << 21)
#define DMA_CTRL_DST_WIDTH_WORD (2UL << 21)
/**
* @name DMA source increment after each transfer.
* @{
*/
#define DMA_CTRL_SRC_NOINC (0UL << 26)
#define DMA_CTRL_SRC_INC (1UL << 26)
/**
* @name DMA destination increment after each transfer.
* @{
*/
#define DMA_CTRL_DST_NOINC (0UL << 27)
#define DMA_CTRL_DST_INC (1UL << 27)
/**
* @name DMA bus access bits.
* @{
*/
#define DMA_CTRL_PROT1_USER (0 << 28)
#define DMA_CTRL_PROT1_PRIV (1UL << 28)
#define DMA_CTRL_PROT2_NONBUFF (0 << 29)
#define DMA_CTRL_PROT2_BUFF (1UL << 29)
#define DMA_CTRL_PROT3_NONCACHE (0 << 30)
#define DMA_CTRL_PROT3_CACHE (1UL << 30)
/** @} */
/**
* @name DMA terminal count interrupt enable.
* @{
*/
#define DMA_CTRL_INT (1UL << 31)
/** @} */
/**
* @name DMA channel enable.
* @{
*/
#define DMA_CFG_CH_ENABLE (1UL << 0)
/**
* @brief Source peripheral.
*
* @param[in] source source peripheral
*/
#define DMA_CFG_SRC_PERIPH(src) ((src) << 1)
/**
* @brief Destination peripheral.
*
* @param[in] destination destination peripheral
*/
#define DMA_CFG_DST_PERIPH(dst) ((dst) << 6)
/**
* @name Transfer type.
* @{
*/
#define DMA_CFG_TTYPE_M2M (0 << 11)
#define DMA_CFG_TTYPE_M2P (1UL << 11)
#define DMA_CFG_TTYPE_P2M (2UL << 11)
#define DMA_CFG_TTYPE_P2P (3UL << 11)
/** @} */
/**
* @name Interrupt error mask.
* @{
*/
#define DMA_CFG_IE (1UL << 14)
/** @} */
/**
* @name Terminal count interrupt mask.
* @{
*/
#define DMA_CFG_ITC (1UL << 15)
/** @} */
/**
* @name Active.
* @note Read only
* @{
*/
#define DMA_CFG_ACTIVE (1UL << 17)
/** @} */
/**
* @name Halt.
* @{
*/
#define DMA_CFG_HALT (1UL << 18)
/** @} */
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @brief DMA interrupt priority level setting.
*/
#if !defined(LPC17xx_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define LPC17xx_DMA_IRQ_PRIORITY 3
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
typedef struct {
volatile uint32_t srcaddr; /**< @brief Source address. */
volatile uint32_t dstaddr; /**< @brief Destination address. */
volatile uint32_t lli; /**< @brief Linked List Item. */
volatile uint32_t control; /**< @brief Control. */
volatile uint32_t config; /**< @brief Configuration. */
} lpc17xx_dma_channel_config_t;
typedef struct {
volatile uint32_t srcaddr; /**< @brief Source address. */
volatile uint32_t dstaddr; /**< @brief Destination address. */
volatile uint32_t lli; /**< @brief Linked List Item. */
volatile uint32_t control; /**< @brief Control. */
} lpc17xx_dma_lli_config_t;
/**
* @brief DMA channel number.
*/
typedef enum {
DMA_CHANNEL0 = 0,
DMA_CHANNEL1 = 1,
DMA_CHANNEL2 = 2,
DMA_CHANNEL3 = 3,
DMA_CHANNEL4 = 4,
DMA_CHANNEL5 = 5,
DMA_CHANNEL6 = 6,
DMA_CHANNEL7 = 7
} lpc17xx_dma_channel_t;
/**
* @brief DMA source or destination type.
*/
typedef enum {
DMA_SSP0_TX = 0,
DMA_SSP0_RX = 1,
DMA_SSP1_TX = 2,
DMA_SSP1_RX = 3,
DMA_ADC = 4,
DMA_I2S_CH0 = 5,
DMA_I2S_CH1 = 6,
DMA_DAC = 7,
DMA_UART0_TX_MAT0_0 = 8,
DMA_UART0_RX_MAT0_1 = 9,
DMA_UART1_TX_MAT1_0 = 10,
DMA_UART1_RX_MAT1_1 = 11,
DMA_UART2_TX_MAT2_0 = 12,
DMA_UART2_RX_MAT2_1 = 13,
DMA_UART3_TX_MAT3_0 = 14,
DMA_UART3_RX_MAT3_1 = 15
} lpc17xx_dma_src_dst_t;
/**
* @brief LPC17xx DMA ISR function type.
*
* @param[in] p parameter for the registered function
* @param[in] flags pre-shifted content of the xISR register, the bits
* are aligned to bit zero
*/
typedef void (*lpc17xx_dmaisr_t)(void *p, uint32_t flags);
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @name Macro Functions
* @{
*/
/**
* @brief Associates a memory source to a DMA channel.
* @note This function can be invoked in both ISR or thread context.
* @pre The channel must have been allocated using @p dmaChannelAllocate().
* @post After use the channel can be released using @p dmaChannelRelease().
*
* @param[in] dmach DMA channel number
* @param[in] addr pointer to a source address
*
* @special
*/
#define dmaChannelSrcAddr(dmach, addr) \
_lpc17xx_dma_channel_config_t[dmach]->CSrcAddr = (uint32_t)(addr)
/**
* @brief Associates a memory destination to a DMA channel.
* @note This function can be invoked in both ISR or thread context.
* @pre The channel must have been allocated using @p dmaChannelAllocate().
* @post After use the channel can be released using @p dmaChannelRelease().
*
* @param[in] dmach DMA channel number
* @param[in] addr pointer to a destination address
*
* @special
*/
#define dmaChannelDstAddr(dmach, addr) \
_lpc17xx_dma_channel_config_t[dmach]->CDestAddr = (uint32_t)(addr)
/**
* @brief Associates a linked list item address to a DMA channel.
* @note This function can be invoked in both ISR or thread context.
* @pre The channel must have been allocated using @p dmaChannelAllocate().
* @post After use the channel can be released using @p dmaChannelRelease().
*
* @param[in] dmach DMA channel number
* @param[in] addr pointer to a linked list item
*
* @special
*/
#define dmaChannelLinkedList(dmach, addr) \
_lpc17xx_dma_channel_config_t[dmach]->CLLI = ((uint32_t)(addr))
/**
* @brief Set control configuration to a DMA channel.
* @note This function can be invoked in both ISR or thread context.
* @pre The channel must have been allocated using @p dmaChannelAllocate().
* @post After use the channel can be released using @p dmaChannelRelease().
*
* @param[in] dmach DMA channel number
* @param[in] ctrl control configuration value
*
* @special
*/
#define dmaChannelControl(dmach, ctrl) \
_lpc17xx_dma_channel_config_t[dmach]->CControl = (ctrl)
/**
* @brief Set configuration to a DMA channel.
* @note This function can be invoked in both ISR or thread context.
* @pre The channel must have been allocated using @p dmaStreamAllocate().
* @post After use the channel can be released using @p dmaStreamRelease().
*
* @param[in] dmach DMA channel number
* @param[in] config dma channel configuration value
*
* @special
*/
#define dmaChannelConfig(dmach, config) \
_lpc17xx_dma_channel_config_t[dmach]->CConfig = (config)
/**
* @brief Trigger DMA software burst transfer request.
*
* @param[in] src peripheral source request
*
* @special
*/
#define dmaSoftBurstRequest(src) \
LPC_GPDMA->SoftBReq = (src)
/**
* @brief Trigger DMA software single transfer request.
*
* @param[in] src peripheral source request
*
* @special
*/
#define dmaSoftSingleRequest(src) \
LPC_GPDMA->SoftSReq = (src)
/**
* @brief DMA channel enable.
* @note This function can be invoked in both ISR or thread context.
* @pre The channel must have been allocated using @p dmaChannelAllocate().
* @post After use the channel can be released using @p dmaChannelRelease().
*
* @param[in] dmach DMA channel number
*
* @special
*/
#define dmaChannelEnable(dmach) \
_lpc17xx_dma_channel_config_t[dmach]->CConfig |= (DMA_CFG_CH_ENABLE)
/**
* @brief DMA channel disable.
* @note This function can be invoked in both ISR or thread context.
* @pre The channel must have been allocated using @p dmaChannelAllocate().
* @post After use the channel can be released using @p dmaChannelRelease().
*
* @param[in] dmach DMA channel number
*
* @special
*/
#define dmaChannelDisable(dmach) \
_lpc17xx_dma_channel_config_t[dmach]->CConfig &= ~(DMA_CFG_CH_ENABLE)
/** @} */
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if !defined(__DOXYGEN__)
extern LPC_GPDMACH_TypeDef * _lpc17xx_dma_channel_config_t[];
#endif
#ifdef __cplusplus
extern "C" {
#endif
void dmaInit(void);
bool_t dmaChannelAllocate(lpc17xx_dma_channel_t dmach,
lpc17xx_dmaisr_t func,
void *param);
void dmaChannelRelease(lpc17xx_dma_channel_t dmach);
#ifdef __cplusplus
}
#endif
#endif /* _LPC17xx_DMA_H_ */
/** @} */
|
