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authorpremek <premysl.vyhnal@gmail.com>2016-08-16 00:44:58 +0200
committerpremek <premysl.vyhnal@gmail.com>2016-08-16 00:44:58 +0200
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tree663ad51b41ff670aa1af4936a5fcb5fdf0df2fcf /lib/lufa/Projects/XPLAINBridge/XPLAINBridge.c
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generated by cgit v1.2.3 (git 2.25.1) at 2025-06-29 11:29:31 +0000
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library ieee;
use ieee.std_logic_1164.all;

entity dff06 is
  port (q : out std_logic;
        d : std_logic;
        en1 : std_logic;
        en2 : std_logic;
        clk : std_logic);
end dff06;

architecture behav of dff06 is
begin
  process (clk) is
  begin
    if (en2 = '1' and en1 = '1') and rising_edge (clk) then
      q <= d;
    end if;
  end process;
end behav;