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/*
             LUFA Library
     Copyright (C) Dean Camera, 2017.

  dean [at] fourwalledcubicle [dot] com
           www.lufa-lib.org
*/

/*
  Copyright 2017  Dean Camera (dean [at] fourwalledcubicle [dot] com)

  Permission to use, copy, modify, distribute, and sell this
  software and its documentation for any purpose is hereby granted
  without fee, provided that the above copyright notice appear in
  all copies and that both that the copyright notice and this
  permission notice and warranty disclaimer appear in supporting
  documentation, and that the name of the author not be used in
  advertising or publicity pertaining to distribution of the
  software without specific, written prior permission.

  The author disclaims all warranties with regard to this
  software, including all implied warranties of merchantability
  and fitness.  In no event shall the author be liable for any
  special, indirect or consequential damages or any damages
  whatsoever resulting from loss of use, data or profits, whether
  in an action of contract, negligence or other tortious action,
  arising out of or in connection with the use or performance of
  this software.
*/

/** \file
 *
 *  Main source file for the MIDI demo. This file contains the main tasks of
 *  the demo and is responsible for the initial application hardware configuration.
 */

#include "MIDI.h"

/** LUFA MIDI Class driver interface configuration and state information. This structure is
 *  passed to all MIDI Class driver functions, so that multiple instances of the same class
 *  within a device can be differentiated from one another.
 */
USB_ClassInfo_MIDI_Device_t Keyboard_MIDI_Interface =
	{
		.Config =
			{
				.StreamingInterfaceNumber = INTERFACE_ID_AudioStream,
				.DataINEndpoint           =
					{
						.Address          = MIDI_STREAM_IN_EPADDR,
						.Size             = MIDI_STREAM_EPSIZE,
						.Banks            = 1,
					},
				.DataOUTEndpoint          =
					{
						.Address          = MIDI_STREAM_OUT_EPADDR,
						.Size             = MIDI_STREAM_EPSIZE,
						.Banks            = 1,
					},
			},
	};


/** Main program entry point. This routine contains the overall program flow, including initial
 *  setup of all components and the main program loop.
 */
int main(void)
{
	SetupHardware();

	LEDs_SetAllLEDs(LEDMASK_USB_NOTREADY);
	GlobalInterruptEnable();

	for (;;)
	{
		CheckJoystickMovement();

		MIDI_EventPacket_t ReceivedMIDIEvent;
		while (MIDI_Device_ReceiveEventPacket(&Keyboard_MIDI_Interface, &ReceivedMIDIEvent))
		{
			if ((ReceivedMIDIEvent.Event == MIDI_EVENT(0, MIDI_COMMAND_NOTE_ON)) && (ReceivedMIDIEvent.Data3 > 0))
			  LEDs_SetAllLEDs(ReceivedMIDIEvent.Data2 > 64 ? LEDS_LED1 : LEDS_LED2);
			else
			  LEDs_SetAllLEDs(LEDS_NO_LEDS);
		}

		MIDI_Device_USBTask(&Keyboard_MIDI_Interface);
		USB_USBTask();
	}
}

/** Configures the board hardware and chip peripherals for the demo's functionality. */
void SetupHardware(void)
{
#if (ARCH == ARCH_AVR8)
	/* Disable watchdog if enabled by bootloader/fuses */
	MCUSR &= ~(1 << WDRF);
	wdt_disable();

	/* Disable clock division */
	clock_prescale_set(clock_div_1);
#elif (ARCH == ARCH_XMEGA)
	/* Start the PLL to multiply the 2MHz RC oscillator to 32MHz and switch the CPU core to run from it */
	XMEGACLK_StartPLL(CLOCK_SRC_INT_RC2MHZ, 2000000, F_CPU);
	XMEGACLK_SetCPUClockSource(CLOCK_SRC_PLL);

	/* Start the 32MHz internal RC oscillator and start the DFLL to increase it to 48MHz using the USB SOF as a reference */
	XMEGACLK_StartInternalOscillator(CLOCK_SRC_INT_RC32MHZ);
	XMEGACLK_StartDFLL(CLOCK_SRC_INT_RC32MHZ, DFLL_REF_INT_USBSOF, F_USB);

	PMIC.CTRL = PMIC_LOLVLEN_bm | PMIC_MEDLVLEN_bm | PMIC_HILVLEN_bm;
#endif

	/* Hardware Initialization */
	Joystick_Init();
	LEDs_Init();
	Buttons_Init();
	USB_Init();
}

/** Checks for changes in the position of the board joystick, sending MIDI events to the host upon each change. */
void CheckJoystickMovement(void)
{
	static uint8_t PrevJoystickStatus;

	uint8_t MIDICommand = 0;
	uint8_t MIDIPitch;

	/* Get current joystick mask, XOR with previous to detect joystick changes */
	uint8_t JoystickStatus  = Joystick_GetStatus();
	uint8_t JoystickChanges = (JoystickStatus ^ PrevJoystickStatus);

	/* Get board button status - if pressed use channel 10 (percussion), otherwise use channel 1 */
	uint8_t Channel = ((Buttons_GetStatus() & BUTTONS_BUTTON1) ? MIDI_CHANNEL(10) : MIDI_CHANNEL(1));

	if (JoystickChanges & JOY_LEFT)
	{
		MIDICommand = ((JoystickStatus & JOY_LEFT)? MIDI_COMMAND_NOTE_ON : MIDI_COMMAND_NOTE_OFF);
		MIDIPitch   = 0x3C;
	}

	if (JoystickChanges & JOY_UP)
	{
		MIDICommand = ((JoystickStatus & JOY_UP)? MIDI_COMMAND_NOTE_ON : MIDI_COMMAND_NOTE_OFF);
		MIDIPitch   = 0x3D;
	}

	if (JoystickChanges & JOY_RIGHT)
	{
		MIDICommand = ((JoystickStatus & JOY_RIGHT)? MIDI_COMMAND_NOTE_ON : MIDI_COMMAND_NOTE_OFF);
		MIDIPitch   = 0x3E;
	}

	if (JoystickChanges & JOY_DOWN)
	{
		MIDICommand = ((JoystickStatus & JOY_DOWN)? MIDI_COMMAND_NOTE_ON : MIDI_COMMAND_NOTE_OFF);
		MIDIPitch   = 0x3F;
	}

	if (JoystickChanges & JOY_PRESS)
	{
		MIDICommand = ((JoystickStatus & JOY_PRESS)? MIDI_COMMAND_NOTE_ON : MIDI_COMMAND_NOTE_OFF);
		MIDIPitch   = 0x3B;
	}

	if (MIDICommand)
	{
		MIDI_EventPacket_t MIDIEvent = (MIDI_EventPacket_t)
			{
				.Event       = MIDI_EVENT(0, MIDICommand),

				.Data1       = MIDICommand | Channel,
				.Data2       = MIDIPitch,
				.Data3       = MIDI_STANDARD_VELOCITY,
			};

		MIDI_Device_SendEventPacket(&Keyboard_MIDI_Interface, &MIDIEvent);
		MIDI_Device_Flush(&Keyboard_MIDI_Interface);
	}

	PrevJoystickStatus = JoystickStatus;
}

/** Event handler for the library USB Connection event. */
void EVENT_USB_Device_Connect(void)
{
	LEDs_SetAllLEDs(LEDMASK_USB_ENUMERATING);
}

/** Event handler for the library USB Disconnection event. */
void EVENT_USB_Device_Disconnect(void)
{
	LEDs_SetAllLEDs(LEDMASK_USB_NOTREADY);
}

/** Event handler for the library USB Configuration Changed event. */
void EVENT_USB_Device_ConfigurationChanged(void)
{
	bool ConfigSuccess = true;

	ConfigSuccess &= MIDI_Device_ConfigureEndpoints(&Keyboard_MIDI_Interface);

	LEDs_SetAllLEDs(ConfigSuccess ? LEDMASK_USB_READY : LEDMASK_USB_ERROR);
}

/** Event handler for the library USB Control Request reception event. */
void EVENT_USB_Device_ControlRequest(void)
{
	MIDI_Device_ProcessControlRequest(&Keyboard_MIDI_Interface);
}
/span> // The following are defines for the bit fields in the CAN_O_ERR register. // //***************************************************************************** #define CAN_ERR_RP 0x00008000 // Received Error Passive #define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter #define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter #define CAN_ERR_REC_S 8 #define CAN_ERR_TEC_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_BIT register. // //***************************************************************************** #define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point #define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point #define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width #define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler #define CAN_BIT_TSEG2_S 12 #define CAN_BIT_TSEG1_S 8 #define CAN_BIT_SJW_S 6 #define CAN_BIT_BRP_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_INT register. // //***************************************************************************** #define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier #define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending #define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_TST register. // //***************************************************************************** #define CAN_TST_RX 0x00000080 // Receive Observation #define CAN_TST_TX_M 0x00000060 // Transmit Control #define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control #define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point #define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low #define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High #define CAN_TST_LBACK 0x00000010 // Loopback Mode #define CAN_TST_SILENT 0x00000008 // Silent Mode #define CAN_TST_BASIC 0x00000004 // Basic Mode //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_BRPE register. // //***************************************************************************** #define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension #define CAN_BRPE_BRPE_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_IF1CRQ register. // //***************************************************************************** #define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag #define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number #define CAN_IF1CRQ_MNUM_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_IF1CMSK register. // //***************************************************************************** #define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read #define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits #define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits #define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits #define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit #define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data #define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request #define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 #define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_IF1MSK1 register. // //***************************************************************************** #define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask #define CAN_IF1MSK1_IDMSK_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_IF1MSK2 register. // //***************************************************************************** #define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier #define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction #define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask #define CAN_IF1MSK2_IDMSK_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_IF1ARB1 register. // //***************************************************************************** #define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier #define CAN_IF1ARB1_ID_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_IF1ARB2 register. // //***************************************************************************** #define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid #define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier #define CAN_IF1ARB2_DIR 0x00002000 // Message Direction #define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier #define CAN_IF1ARB2_ID_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_IF1MCTL register. // //***************************************************************************** #define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data #define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost #define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending #define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask #define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable #define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable #define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable #define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request #define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer #define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code #define CAN_IF1MCTL_DLC_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_IF1DA1 register. // //***************************************************************************** #define CAN_IF1DA1_DATA_M 0x0000FFFF // Data #define CAN_IF1DA1_DATA_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_IF1DA2 register. // //***************************************************************************** #define CAN_IF1DA2_DATA_M 0x0000FFFF // Data #define CAN_IF1DA2_DATA_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_IF1DB1 register. // //***************************************************************************** #define CAN_IF1DB1_DATA_M 0x0000FFFF // Data #define CAN_IF1DB1_DATA_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_IF1DB2 register. // //***************************************************************************** #define CAN_IF1DB2_DATA_M 0x0000FFFF // Data #define CAN_IF1DB2_DATA_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_IF2CRQ register. // //***************************************************************************** #define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag #define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number #define CAN_IF2CRQ_MNUM_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_IF2CMSK register. // //***************************************************************************** #define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read #define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits #define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits #define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits #define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit #define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data #define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request #define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 #define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_IF2MSK1 register. // //***************************************************************************** #define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask #define CAN_IF2MSK1_IDMSK_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_IF2MSK2 register. // //***************************************************************************** #define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier #define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction #define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask #define CAN_IF2MSK2_IDMSK_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_IF2ARB1 register. // //***************************************************************************** #define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier #define CAN_IF2ARB1_ID_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_IF2ARB2 register. // //***************************************************************************** #define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid #define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier #define CAN_IF2ARB2_DIR 0x00002000 // Message Direction #define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier #define CAN_IF2ARB2_ID_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_IF2MCTL register. // //***************************************************************************** #define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data #define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost #define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending #define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask #define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable #define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable #define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable #define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request #define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer #define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code #define CAN_IF2MCTL_DLC_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_IF2DA1 register. // //***************************************************************************** #define CAN_IF2DA1_DATA_M 0x0000FFFF // Data #define CAN_IF2DA1_DATA_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_IF2DA2 register. // //***************************************************************************** #define CAN_IF2DA2_DATA_M 0x0000FFFF // Data #define CAN_IF2DA2_DATA_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_IF2DB1 register. // //***************************************************************************** #define CAN_IF2DB1_DATA_M 0x0000FFFF // Data #define CAN_IF2DB1_DATA_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_IF2DB2 register. // //***************************************************************************** #define CAN_IF2DB2_DATA_M 0x0000FFFF // Data #define CAN_IF2DB2_DATA_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_TXRQ1 register. // //***************************************************************************** #define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits #define CAN_TXRQ1_TXRQST_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_TXRQ2 register. // //***************************************************************************** #define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits #define CAN_TXRQ2_TXRQST_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_NWDA1 register. // //***************************************************************************** #define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits #define CAN_NWDA1_NEWDAT_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_NWDA2 register. // //***************************************************************************** #define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits #define CAN_NWDA2_NEWDAT_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_MSG1INT register. // //***************************************************************************** #define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits #define CAN_MSG1INT_INTPND_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_MSG2INT register. // //***************************************************************************** #define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits #define CAN_MSG2INT_INTPND_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_MSG1VAL register. // //***************************************************************************** #define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits #define CAN_MSG1VAL_MSGVAL_S 0 //***************************************************************************** // // The following are defines for the bit fields in the CAN_O_MSG2VAL register. // //***************************************************************************** #define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits #define CAN_MSG2VAL_MSGVAL_S 0 #endif // __HW_CAN_H__