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| author | inmarket <andrewh@inmarket.com.au> | 2014-12-15 18:17:52 +1000 |
|---|---|---|
| committer | inmarket <andrewh@inmarket.com.au> | 2014-12-15 18:17:52 +1000 |
| commit | 3936c630612c9aff74f3bc21984e486f81d3f7da (patch) | |
| tree | 029522b7742fc23ec6a754077cfab7b16f46142e /boards/base/Embest-STM32-DMSTF4BB | |
| parent | 21a26eb7620553f4c822c7cc5fb450c0a00649e5 (diff) | |
| download | uGFX-3936c630612c9aff74f3bc21984e486f81d3f7da.tar.gz uGFX-3936c630612c9aff74f3bc21984e486f81d3f7da.tar.bz2 uGFX-3936c630612c9aff74f3bc21984e486f81d3f7da.zip | |
Updates for the EMBEST board and a small fix to the SSD2119 driver.
Diffstat (limited to 'boards/base/Embest-STM32-DMSTF4BB')
| -rw-r--r-- | boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h | 11 | ||||
| -rw-r--r-- | boards/base/Embest-STM32-DMSTF4BB/gmouse_lld_STMPE811_board.h | 2 |
2 files changed, 8 insertions, 5 deletions
diff --git a/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h b/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h index 2b1aa27d..a8b42239 100644 --- a/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h +++ b/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h @@ -29,8 +29,8 @@ * the PWM frequency should be somewhere between 200 Hz to 200 kHz. */ static const PWMConfig pwmcfg = { - 1000000, /* 1 MHz PWM clock frequency. */ - 100, /* PWM period is 100 cycles. */ + 20000, /* 20 KHz PWM clock frequency. */ + 100, /* PWM period is 100 cycles. */ 0, { {PWM_OUTPUT_ACTIVE_HIGH, 0}, @@ -75,8 +75,11 @@ static inline void init_board(GDisplay *g) { palSetBusMode(&busE, PAL_MODE_ALTERNATE(12)); /* FSMC timing register configuration */ - FSMC_Bank1->BTCR[0 + 1] = (FSMC_BTR1_ADDSET_2 | FSMC_BTR1_ADDSET_1) \ - | (FSMC_BTR1_DATAST_2 | FSMC_BTR1_DATAST_1) \ +// FSMC_Bank1->BTCR[0 + 1] = (FSMC_BTR1_ADDSET_2 | FSMC_BTR1_ADDSET_1) \ +// | (FSMC_BTR1_DATAST_2 | FSMC_BTR1_DATAST_1) \ +// | FSMC_BTR1_BUSTURN_0; + FSMC_Bank1->BTCR[0 + 1] = (FSMC_BTR1_ADDSET_3 | FSMC_BTR1_ADDSET_0) \ + | (FSMC_BTR1_DATAST_3 | FSMC_BTR1_DATAST_0) \ | FSMC_BTR1_BUSTURN_0; /* Bank1 NOR/PSRAM control register configuration diff --git a/boards/base/Embest-STM32-DMSTF4BB/gmouse_lld_STMPE811_board.h b/boards/base/Embest-STM32-DMSTF4BB/gmouse_lld_STMPE811_board.h index bbb17010..43a8ad18 100644 --- a/boards/base/Embest-STM32-DMSTF4BB/gmouse_lld_STMPE811_board.h +++ b/boards/base/Embest-STM32-DMSTF4BB/gmouse_lld_STMPE811_board.h @@ -39,7 +39,7 @@ static const I2CConfig i2ccfg = { OPMODE_I2C, - 400000, + 200000, // Conservative please FAST_DUTY_CYCLE_2, }; |