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author | inmarket <andrewh@inmarket.com.au> | 2018-11-03 10:51:23 +1000 |
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committer | inmarket <andrewh@inmarket.com.au> | 2018-11-03 10:51:23 +1000 |
commit | 7c5a6c928fa7129cf754c9c73c5c7ae39372ba9d (patch) | |
tree | 95cf152ef65ff19c7b2515b427bbe86b92b611d0 /boards/base/STM32F746-Discovery/example_raw32 | |
parent | 8bd70d953bcd3e32ceb4e45a4e561c973726280a (diff) | |
download | uGFX-7c5a6c928fa7129cf754c9c73c5c7ae39372ba9d.tar.gz uGFX-7c5a6c928fa7129cf754c9c73c5c7ae39372ba9d.tar.bz2 uGFX-7c5a6c928fa7129cf754c9c73c5c7ae39372ba9d.zip |
For all source files update integer types to the new gI8 etc type names
Diffstat (limited to 'boards/base/STM32F746-Discovery/example_raw32')
-rw-r--r-- | boards/base/STM32F746-Discovery/example_raw32/stm32f7xx_hal_conf.h | 76 |
1 files changed, 38 insertions, 38 deletions
diff --git a/boards/base/STM32F746-Discovery/example_raw32/stm32f7xx_hal_conf.h b/boards/base/STM32F746-Discovery/example_raw32/stm32f7xx_hal_conf.h index bedea770..94c2d2e4 100644 --- a/boards/base/STM32F746-Discovery/example_raw32/stm32f7xx_hal_conf.h +++ b/boards/base/STM32F746-Discovery/example_raw32/stm32f7xx_hal_conf.h @@ -100,11 +100,11 @@ * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE ((gU32)25000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT ((gU32)100U) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -113,14 +113,14 @@ * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ + #define HSI_VALUE ((gU32)16000000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** * @brief Internal Low Speed oscillator (LSI) value. */ #if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ + #define LSI_VALUE ((gU32)32000U) /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. */ @@ -128,11 +128,11 @@ * @brief External Low Speed oscillator (LSE) value. */ #if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ + #define LSE_VALUE ((gU32)32768U) /*!< Value of the External Low Speed oscillator in Hz */ #endif /* LSE_VALUE */ #if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ + #define LSE_STARTUP_TIMEOUT ((gU32)5000U) /*!< Time out for LSE start up, in ms */ #endif /* LSE_STARTUP_TIMEOUT */ /** @@ -141,7 +141,7 @@ * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ + #define EXTERNAL_CLOCK_VALUE ((gU32)12288000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* EXTERNAL_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, @@ -151,8 +151,8 @@ /** * @brief This is the HAL system configuration section */ -#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */ +#define VDD_VALUE ((gU32)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((gU32)0x0F) /*!< tick interrupt priority */ #define USE_RTOS 0 #define ART_ACCLERATOR_ENABLE 1 /* To enable instruction cache and prefetch */ @@ -178,50 +178,50 @@ /* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB ((uint32_t)5U) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB ((uint32_t)5U) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ +#define ETH_RXBUFNB ((gU32)5U) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((gU32)5U) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ /* Section 2: PHY configuration section */ /* LAN8742A PHY Address*/ #define LAN8742A_PHY_ADDRESS 0x00U /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY ((uint32_t)0x00000FFFU) +#define PHY_RESET_DELAY ((gU32)0x00000FFFU) /* PHY Configuration delay */ -#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) +#define PHY_CONFIG_DELAY ((gU32)0x00000FFFU) -#define PHY_READ_TO ((uint32_t)0x0000FFFFU) -#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) +#define PHY_READ_TO ((gU32)0x0000FFFFU) +#define PHY_WRITE_TO ((gU32)0x0000FFFFU) /* Section 3: Common PHY Registers */ -#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ +#define PHY_BCR ((gU16)0x00U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((gU16)0x01U) /*!< Transceiver Basic Status Register */ -#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ +#define PHY_RESET ((gU16)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((gU16)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((gU16)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((gU16)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((gU16)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((gU16)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((gU16)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((gU16)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((gU16)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((gU16)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((gU16)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((gU16)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((gU16)0x0002U) /*!< Jabber condition detected */ /* Section 4: Extended PHY Registers */ -#define PHY_SR ((uint16_t)0x1FU) /*!< PHY special control/ status register Offset */ +#define PHY_SR ((gU16)0x1FU) /*!< PHY special control/ status register Offset */ -#define PHY_SPEED_STATUS ((uint16_t)0x0004U) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0010U) /*!< PHY Duplex mask */ +#define PHY_SPEED_STATUS ((gU16)0x0004U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((gU16)0x0010U) /*!< PHY Duplex mask */ -#define PHY_ISFR ((uint16_t)0x1DU) /*!< PHY Interrupt Source Flag register Offset */ -#define PHY_ISFR_INT4 ((uint16_t)0x0010U) /*!< PHY Link down inturrupt */ +#define PHY_ISFR ((gU16)0x1DU) /*!< PHY Interrupt Source Flag register Offset */ +#define PHY_ISFR_INT4 ((gU16)0x0010U) /*!< PHY Link down inturrupt */ /* ################## SPI peripheral configuration ########################## */ @@ -407,9 +407,9 @@ * If expr is true, it returns no value. * @retval None */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((gU8 *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); + void assert_failed(gU8* file, gU32 line); #else #define assert_param(expr) ((void)0) #endif /* USE_FULL_ASSERT */ |