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path: root/docs/cryptography-docs.py
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# This file is dual licensed under the terms of the Apache License, Version
# 2.0, and the BSD License. See the LICENSE file in the root of this repository
# for complete details.

from __future__ import absolute_import, division, print_function

from docutils import nodes

from sphinx.util.compat import Directive


DANGER_MESSAGE = """
This is a "Hazardous Materials" module. You should **ONLY** use it if you're
100% absolutely sure that you know what you're doing because this module is
full of land mines, dragons, and dinosaurs with laser guns.
"""

DANGER_ALTERNATE = """

You may instead be interested in :doc:`{alternate}`.
"""


class HazmatDirective(Directive):
    has_content = True

    def run(self):
        message = DANGER_MESSAGE
        if self.content:
            message += DANGER_ALTERNATE.format(alternate=self.content[0])

        content = nodes.paragraph("", message)
        admonition_node = Hazmat("\n".join(content))
        self.state.nested_parse(content, self.content_offset, admonition_node)
        admonition_node.line = self.lineno
        return [admonition_node]


class Hazmat(nodes.Admonition, nodes.Element):
    pass


def html_visit_hazmat_node(self, node):
    return self.visit_admonition(node, "danger")


def latex_visit_hazmat_node(self, node):
    return self.visit_admonition(node)


def depart_hazmat_node(self, node):
    return self.depart_admonition(node)


def setup(app):
    app.add_node(
        Hazmat,
        html=(html_visit_hazmat_node, depart_hazmat_node),
        latex=(latex_visit_hazmat_node, depart_hazmat_node),
    )
    app.add_directive("hazmat", HazmatDirective)

    return {
        "parallel_read_safe": True,
    }
* Window 0 is the default window and is the only window enabled upon reset. * The default outbound register set is used when a transaction misses * in all of the other outbound windows. */ struct pci_outbound_window_regs pow[5]; u8 res14[96]; struct pci_inbound_window_regs pmit; /* 0xd00 - 0xd9c Inbound MSI */ u8 res6[96]; /* PCI/PCI Express inbound window 3-0 * inbound window 1 supports only a 32-bit base address and does not * define an inbound window base extended address register. */ struct pci_inbound_window_regs piw[4]; __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */ u8 res21[4]; __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */ u8 res22[4]; __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */ u8 res23[12]; __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */ u8 res24[4]; __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */ __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */ __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */ __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */ }; extern int fsl_add_bridge(struct device_node *dev, int is_primary); extern void fsl_pcibios_fixup_bus(struct pci_bus *bus); extern int mpc83xx_add_bridge(struct device_node *dev); u64 fsl_pci_immrbar_base(struct pci_controller *hose); #endif /* __POWERPC_FSL_PCI_H */ #endif /* __KERNEL__ */