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author	Maximilian Hils <git@maximilianhils.com>	2017-04-30 18:26:41 +0200
committer	GitHub <noreply@github.com>	2017-04-30 18:26:41 +0200
commit	288448c5755e098a1f632b7ba13c0c62e0e8f0b7 (patch)
tree	01bf68690775e348a18d97d31e48e27741c8bd20 /web/src/js/components/FlowTable/FlowColumns.jsx
parent	fccc9bc45ef55e3e7f14ee4a51f376c53b418991 (diff)
parent	365677006cc9f749a59ce5b5cf9b13d50dca8c0f (diff)
download	mitmproxy-288448c5755e098a1f632b7ba13c0c62e0e8f0b7.tar.gz mitmproxy-288448c5755e098a1f632b7ba13c0c62e0e8f0b7.tar.bz2 mitmproxy-288448c5755e098a1f632b7ba13c0c62e0e8f0b7.zip

Merge pull request #2285 from MatthewShao/jest-dev

[web] Add coverage for js/urlState.js

Diffstat (limited to 'web/src/js/components/FlowTable/FlowColumns.jsx')

0 files changed, 0 insertions, 0 deletions

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From edff8f777c6321ca89bb950a382f409c4a126e28 Mon Sep 17 00:00:00 2001
From: Gokul Sriram Palanisamy <gpalan@codeaurora.org>
Date: Thu, 15 Dec 2016 17:38:18 +0530
Subject: pcie: Set PCIE MRRS and MPS to 256B

Set Max Read Request Size and Max Payload Size to 256 bytes,
per chip team recommendation.

Change-Id: I097004be2ced1b3096ffc10c318aae0b2bb155e8
Signed-off-by: Gokul Sriram Palanisamy <gpalan@codeaurora.org>
---
 drivers/pci/host/pcie-qcom.c | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

(limited to 'drivers/pci/host/pcie-qcom.c')

--- a/drivers/pci/host/pcie-qcom.c
+++ b/drivers/pci/host/pcie-qcom.c
@@ -92,6 +92,14 @@
 
 #define PCIE20_LNK_CONTROL2_LINK_STATUS2        0xA0
 
+#define __set(v, a, b)	(((v) << (b)) & GENMASK(a, b))
+#define __mask(a, b)	(((1 << ((a) + 1)) - 1) & ~((1 << (b)) - 1))
+#define PCIE20_DEV_CAS			0x78
+#define PCIE20_MRRS_MASK		__mask(14, 12)
+#define PCIE20_MRRS(x)			__set(x, 14, 12)
+#define PCIE20_MPS_MASK			__mask(7, 5)
+#define PCIE20_MPS(x)			__set(x, 7, 5)
+
 struct qcom_pcie_resources_v0 {
 	struct clk *iface_clk;
 	struct clk *core_clk;
@@ -745,6 +753,35 @@ static int qcom_pcie_probe(struct platfo
 	return 0;
 }
 
+static void qcom_pcie_fixup_final(struct pci_dev *dev)
+{
+	int cap, err;
+	u16 ctl, reg_val;
+
+	cap = pci_pcie_cap(dev);
+	if (!cap)
+		return;
+
+	err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
+
+	if (err)
+		return;
+
+	reg_val = ctl;
+
+	if (((reg_val & PCIE20_MRRS_MASK) >> 12) > 1)
+		reg_val = (reg_val & ~(PCIE20_MRRS_MASK)) | PCIE20_MRRS(0x1);
+
+	if (((ctl & PCIE20_MPS_MASK) >> 5) > 1)
+		reg_val = (reg_val & ~(PCIE20_MPS_MASK)) | PCIE20_MPS(0x1);
+
+	err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, reg_val);
+
+	if (err)
+		pr_err("pcie config write failed %d\n", err);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, qcom_pcie_fixup_final);
+
 static const struct of_device_id qcom_pcie_match[] = {
 	{ .compatible = "qcom,pcie-ipq8064", .data = &ops_v0 },
 	{ .compatible = "qcom,pcie-apq8064", .data = &ops_v0 },


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