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As discussed in [the Flow View section of the mitmproxy
overview](@!urlTo("mitmproxy.html")!@), mitmproxy allows you to inspect and
manipulate flows.  When inspecting a single flow, mitmproxy uses a number of
heuristics to show a friendly view of various content types; if mitmproxy
cannot show a friendly view, mitmproxy defaults to a __raw__ view.

Each content type invokes a different flow viewer to parse the data and display
the friendly view. Users can add custom content viewers by adding a view class
to contentview.py, discussed below.

## Adding a new View class to contentview.py

The content viewers used by mitmproxy to present a friendly view of various
content types are stored in contentview.py.  Reviewing this file shows a number
of classes named ViewSomeDataType, each with the properties: __name__,
__prompt__, and __content\_types__ and a function named __\_\_call\_\___.

Adding a new content viewer to parse a data type is as simple as writing a new
View class.  Your new content viewer View class should have the same properties
as the other View classes: __name__, __prompt__, and __content\_types__ and a
__\_\_call\_\___ function to parse the content of the request/response. 

* The __name__ property should be a string describing the contents and new content viewer; 
* The __prompt__ property should be a two item tuple:

  - __1__: A string that will be used to display the new content viewer's type; and
  - __2__: A one character string that will be the hotkey used to select the new content viewer from the Flow View screen; 

* The __content\_types__ property should be a list of strings of HTTP Content\-Types that the new content viewer can parse.  
  * Note that mitmproxy will use the content\_types to try and heuristically show a friendly view of content and that you can override the built-in views by populating content\_types with values for content\_types that are already parsed -- e.g. "image/png".

After defining the __name__, __prompt__, and __content\_types__ properties of
the class, you should write the __\_\_call\_\___ function, which will parse the
request/response data and provide a friendly view of the data.  The
__\_\_call\_\___ function should take the following arguments: __self__,
__hdrs__, __content__, __limit__; __hdrs__ is a ODictCaseless object containing
the headers of the request/response; __content__ is the content of the
request/response, and __limit__ is an integer representing the amount of data
to display in the view window.

The __\_\_call\_\___ function returns two values: (1) a string describing the
parsed data; and (2) the parsed data for friendly display.  The parsed data to
be displayed should be a list of strings formatted for display.  You can use
the __\_view\_text__ function in contentview.py to format text for display.
Alternatively, you can display content as a series of key-value pairs; to do
so, prepare a list of lists, where each list item is a two item list -- a key
that describes the data, and then the data itself; after preparing the list of
lists, use the __common.format\_keyvals__ function on it to prepare it as text
for display.  

If the new content viewer fails or throws an exception, mitmproxy will default
to a __raw__ view.
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/* -*-  Mode:C; c-basic-offset:4; tab-width:4; indent-tabs-mode:nil -*- */
/*
 * mmio.c: MMIO emulation components.
 * Copyright (c) 2004, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 * Place - Suite 330, Boston, MA 02111-1307 USA.
 *
 *  Yaozu Dong (Eddie Dong) (Eddie.dong@intel.com)
 *  Kun Tian (Kevin Tian) (Kevin.tian@intel.com)
 */

#include <linux/sched.h>
#include <xen/mm.h>
#include <asm/tlb.h>
#include <asm/vmx_mm_def.h>
#include <asm/gcc_intrin.h>
#include <linux/interrupt.h>
#include <asm/vmx_vcpu.h>
#include <asm/bundle.h>
#include <asm/types.h>
#include <public/hvm/ioreq.h>
#include <asm/vmx.h>
#include <public/event_channel.h>
#include <public/xen.h>
#include <linux/event.h>
#include <xen/domain.h>
/*
struct mmio_list *lookup_mmio(u64 gpa, struct mmio_list *mio_base)
{
    int     i;
    for (i=0; mio_base[i].iot != NOT_IO; i++ ) {
        if ( gpa >= mio_base[i].start && gpa <= mio_base[i].end )
            return &mio_base[i];
    }
    return NULL;
}
*/

#define	PIB_LOW_HALF(ofst)	!(ofst&(1<<20))
#define PIB_OFST_INTA           0x1E0000
#define PIB_OFST_XTP            0x1E0008

#define HVM_BUFFERED_IO_RANGE_NR 1

struct hvm_buffered_io_range {
    unsigned long start_addr;
    unsigned long length;
};

static struct hvm_buffered_io_range buffered_stdvga_range = {0xA0000, 0x20000};
static struct hvm_buffered_io_range
*hvm_buffered_io_ranges[HVM_BUFFERED_IO_RANGE_NR] =
{
    &buffered_stdvga_range
};

int hvm_buffered_io_intercept(ioreq_t *p)
{
    struct vcpu *v = current;
    spinlock_t  *buffered_io_lock;
    buffered_iopage_t *buffered_iopage =
        (buffered_iopage_t *)(v->domain->arch.hvm_domain.buffered_io_va);
    unsigned long tmp_write_pointer = 0;
    int i;

    /* ignore READ ioreq_t! */
    if ( p->dir == IOREQ_READ )
        return 0;

    for ( i = 0; i < HVM_BUFFERED_IO_RANGE_NR; i++ ) {
        if ( p->addr >= hvm_buffered_io_ranges[i]->start_addr &&
             p->addr + p->size - 1 < hvm_buffered_io_ranges[i]->start_addr +
                                     hvm_buffered_io_ranges[i]->length )
            break;
    }

    if ( i == HVM_BUFFERED_IO_RANGE_NR )
        return 0;

    buffered_io_lock = &v->domain->arch.hvm_domain.buffered_io_lock;
    spin_lock(buffered_io_lock);

    if ( buffered_iopage->write_pointer - buffered_iopage->read_pointer ==
         (unsigned long)IOREQ_BUFFER_SLOT_NUM ) {
        /* the queue is full.
         * send the iopacket through the normal path.
         * NOTE: The arithimetic operation could handle the situation for
         * write_pointer overflow.
         */
        spin_unlock(buffered_io_lock);
        return 0;
    }

    tmp_write_pointer = buffered_iopage->write_pointer % IOREQ_BUFFER_SLOT_NUM;

    memcpy(&buffered_iopage->ioreq[tmp_write_pointer], p, sizeof(ioreq_t));

    /*make the ioreq_t visible before write_pointer*/
    wmb();
    buffered_iopage->write_pointer++;

    spin_unlock(buffered_io_lock);

    return 1;
}

static void write_ipi (VCPU *vcpu, uint64_t addr, uint64_t value);

static void pib_write(VCPU *vcpu, void *src, uint64_t pib_off, size_t s, int ma)
{
    switch (pib_off) {
    case PIB_OFST_INTA:
        panic_domain(NULL,"Undefined write on PIB INTA\n");
        break;
    case PIB_OFST_XTP:
        if ( s == 1 && ma == 4 /* UC */) {
            vmx_vcpu_get_plat(vcpu)->xtp = *(uint8_t *)src;
        }
        else {
            panic_domain(NULL,"Undefined write on PIB XTP\n");
        }
        break;
    default:
        if ( PIB_LOW_HALF(pib_off) ) {   // lower half
            if ( s != 8 || ma != 0x4 /* UC */ ) {
                panic_domain
		  (NULL,"Undefined IPI-LHF write with s %ld, ma %d!\n", s, ma);
            }
            else {
                write_ipi(vcpu, pib_off, *(uint64_t *)src);
                // TODO for SM-VP
            }
        }
        else {      // upper half
            printk("IPI-UHF write %lx\n",pib_off);
            panic_domain(NULL,"Not support yet for SM-VP\n");
        }
        break;
    }
}

static void pib_read(VCPU *vcpu, uint64_t pib_off, void *dest, size_t s, int ma)
{
    switch (pib_off) {
    case PIB_OFST_INTA:
        // todo --- emit on processor system bus.
        if ( s == 1 && ma == 4) { // 1 byte load
            // TODO: INTA read from IOSAPIC
        }
        else {
            panic_domain(NULL,"Undefined read on PIB INTA\n");
        }
        break;
    case PIB_OFST_XTP:
        if ( s == 1 && ma == 4) {
            *((uint8_t*)dest) = vmx_vcpu_get_plat(vcpu)->xtp;
        }
        else {
            panic_domain(NULL,"Undefined read on PIB XTP\n");
        }
        break;
    default:
        if ( PIB_LOW_HALF(pib_off) ) {   // lower half
            if ( s != 8 || ma != 4 ) {
                panic_domain(NULL,"Undefined IPI-LHF read!\n");
            }
            else {
#ifdef  IPI_DEBUG
                printk("IPI-LHF read %lx\n",pib_off);
#endif
                *(uint64_t *)dest = 0;  // TODO for SM-VP
            }
        }
        else {      // upper half
            if ( s != 1 || ma != 4 ) {
                panic_domain(NULL,"Undefined PIB-UHF read!\n");
            }
            else {
#ifdef  IPI_DEBUG
                printk("IPI-UHF read %lx\n",pib_off);
#endif
                *(uint8_t *)dest = 0;   // TODO for SM-VP
            }
        }
        break;
    }
}

static void low_mmio_access(VCPU *vcpu, u64 pa, u64 *val, size_t s, int dir)
{
    struct vcpu *v = current;
    vcpu_iodata_t *vio;
    ioreq_t *p;

    vio = get_vio(v->domain, v->vcpu_id);
    if (vio == 0) {
        panic_domain(NULL,"bad shared page: %lx", (unsigned long)vio);
    }
    p = &vio->vp_ioreq;
    p->addr = pa;
    p->size = s;
    p->count = 1;
    p->dir = dir;
    if(dir==IOREQ_WRITE)     //write;
        p->u.data = *val;
    p->pdata_valid = 0;
    p->type = 1;
    p->df = 0;

    p->io_count++;
    if(hvm_buffered_io_intercept(p)){
        p->state = STATE_IORESP_READY;
        vmx_io_assist(v);
        return ;
    }else 
    vmx_send_assist_req(v);
    if(dir==IOREQ_READ){ //read
        *val=p->u.data;
    }
    return;
}
#define TO_LEGACY_IO(pa)  (((pa)>>12<<2)|((pa)&0x3))

static void legacy_io_access(VCPU *vcpu, u64 pa, u64 *val, size_t s, int dir)
{
    struct vcpu *v = current;
    vcpu_iodata_t *vio;
    ioreq_t *p;

    vio = get_vio(v->domain, v->vcpu_id);
    if (vio == 0) {
        panic_domain(NULL,"bad shared page\n");
    }
    p = &vio->vp_ioreq;
    p->addr = TO_LEGACY_IO(pa&0x3ffffffUL);
    p->size = s;
    p->count = 1;
    p->dir = dir;
    if(dir==IOREQ_WRITE)     //write;
        p->u.data = *val;
    p->pdata_valid = 0;
    p->type = 0;
    p->df = 0;

    p->io_count++;

    vmx_send_assist_req(v);
    if(dir==IOREQ_READ){ //read
        *val=p->u.data;
    }
#ifdef DEBUG_PCI
    if(dir==IOREQ_WRITE)
        if(p->addr == 0xcf8UL)
            printk("Write 0xcf8, with val [0x%lx]\n", p->u.data);
    else
        if(p->addr == 0xcfcUL)
            printk("Read 0xcfc, with val [0x%lx]\n", p->u.data);
#endif //DEBUG_PCI
    return;
}

extern struct vmx_mmio_handler vioapic_mmio_handler;
static void mmio_access(VCPU *vcpu, u64 src_pa, u64 *dest, size_t s, int ma, int dir)
{
    struct virtual_platform_def *v_plat;
    //mmio_type_t iot;
    unsigned long iot;
    struct vmx_mmio_handler *vioapic_handler = &vioapic_mmio_handler;
    iot=__gpfn_is_io(vcpu->domain, src_pa>>PAGE_SHIFT);
    v_plat = vmx_vcpu_get_plat(vcpu);

    perfc_incra(vmx_mmio_access, iot >> 56);
    switch (iot) {
    case GPFN_PIB:
        if(!dir)
            pib_write(vcpu, dest, src_pa - v_plat->pib_base, s, ma);
        else
            pib_read(vcpu, src_pa - v_plat->pib_base, dest, s, ma);
        break;
    case GPFN_GFW:
        break;
    case GPFN_IOSAPIC:
	if (!dir)
	    vioapic_handler->write_handler(vcpu, src_pa, s, *dest);
	else
	    *dest = vioapic_handler->read_handler(vcpu, src_pa, s);
	break;
    case GPFN_FRAME_BUFFER:
    case GPFN_LOW_MMIO:
        low_mmio_access(vcpu, src_pa, dest, s, dir);
        break;
    case GPFN_LEGACY_IO:
        legacy_io_access(vcpu, src_pa, dest, s, dir);
        break;
    default:
        panic_domain(NULL,"Bad I/O access\n");
        break;
    }
    return;
}

/*
 * Read or write data in guest virtual address mode.
 */
/*
void
memwrite_v(VCPU *vcpu, thash_data_t *vtlb, u64 *src, u64 *dest, size_t s)
{
    uint64_t pa;

    if (!vtlb->nomap)
        panic("Normal memory write shouldn't go to this point!");
    pa = PPN_2_PA(vtlb->ppn);
    pa += POFFSET((u64)dest, vtlb->ps);
    mmio_write (vcpu, src, pa, s, vtlb->ma);
}


void
memwrite_p(VCPU *vcpu, u64 *src, u64 *dest, size_t s)
{
    uint64_t pa = (uint64_t)dest;
    int    ma;

    if ( pa & (1UL <<63) ) {
        // UC
        ma = 4;
        pa <<=1;
        pa >>=1;
    }
    else {
        // WBL
        ma = 0;     // using WB for WBL
    }
    mmio_write (vcpu, src, pa, s, ma);
}

void
memread_v(VCPU *vcpu, thash_data_t *vtlb, u64 *src, u64 *dest, size_t s)
{
    uint64_t pa;

    if (!vtlb->nomap)
        panic_domain(NULL,"Normal memory write shouldn't go to this point!");
    pa = PPN_2_PA(vtlb->ppn);
    pa += POFFSET((u64)src, vtlb->ps);

    mmio_read(vcpu, pa, dest, s, vtlb->ma);
}

void
memread_p(VCPU *vcpu, u64 *src, u64 *dest, size_t s)
{
    uint64_t pa = (uint64_t)src;
    int    ma;

    if ( pa & (1UL <<63) ) {
        // UC
        ma = 4;
        pa <<=1;
        pa >>=1;
    }
    else {
        // WBL
        ma = 0;     // using WB for WBL
    }
    mmio_read(vcpu, pa, dest, s, ma);
}
*/


/*
 * Deliver IPI message. (Only U-VP is supported now)
 *  offset: address offset to IPI space.
 *  value:  deliver value.
 */
static void deliver_ipi (VCPU *vcpu, uint64_t dm, uint64_t vector)
{
#ifdef  IPI_DEBUG
  printk ("deliver_ipi %lx %lx\n",dm,vector);
#endif
    switch ( dm ) {
    case 0:     // INT
        vmx_vcpu_pend_interrupt (vcpu, vector);
        break;
    case 2:     // PMI
        // TODO -- inject guest PMI
        panic_domain (NULL, "Inject guest PMI!\n");
        break;
    case 4:     // NMI
        vmx_vcpu_pend_interrupt (vcpu, 2);
        break;
    case 5:     // INIT
        // TODO -- inject guest INIT
        panic_domain (NULL, "Inject guest INIT!\n");
        break;
    case 7:     // ExtINT
        vmx_vcpu_pend_interrupt (vcpu, 0);
        break;
    case 1:
    case 3:
    case 6:
    default:
        panic_domain (NULL, "Deliver reserved IPI!\n");
        break;
    }
}

/*
 * TODO: Use hash table for the lookup.
 */
static inline VCPU *lid_2_vcpu (struct domain *d, u64 id, u64 eid)
{
    int   i;
    VCPU  *vcpu;
    LID   lid;
    for (i=0; i<MAX_VIRT_CPUS; i++) {
        vcpu = d->vcpu[i];
        if (!vcpu)
            continue;
        lid.val = VCPU_LID(vcpu);
        if ( lid.id == id && lid.eid == eid )
            return vcpu;
    }
    return NULL;
}

/*
 * execute write IPI op.
 */
static void write_ipi (VCPU *vcpu, uint64_t addr, uint64_t value)
{
    VCPU   *targ;
    struct domain *d=vcpu->domain; 
    targ = lid_2_vcpu(vcpu->domain, 
           ((ipi_a_t)addr).id, ((ipi_a_t)addr).eid);
    if ( targ == NULL ) panic_domain (NULL,"Unknown IPI cpu\n");

    if (!test_bit(_VCPUF_initialised, &targ->vcpu_flags)) {
        struct pt_regs *targ_regs = vcpu_regs (targ);
        struct vcpu_guest_context c;

        memset (&c, 0, sizeof (c));

        if (arch_set_info_guest (targ, &c) != 0) {
            printk ("arch_boot_vcpu: failure\n");
            return;
        }
        /* First or next rendez-vous: set registers.  */
        vcpu_init_regs (targ);
        targ_regs->cr_iip = d->arch.sal_data->boot_rdv_ip;
        targ_regs->r1 = d->arch.sal_data->boot_rdv_r1;

        if (test_and_clear_bit(_VCPUF_down,&targ->vcpu_flags)) {
            vcpu_wake(targ);
            printk ("arch_boot_vcpu: vcpu %d awaken %016lx!\n",
                    targ->vcpu_id, targ_regs->cr_iip);
        }
        else
            printk ("arch_boot_vcpu: huu, already awaken!");
    }
    else {
        int running = test_bit(_VCPUF_running,&targ->vcpu_flags);
        deliver_ipi (targ, ((ipi_d_t)value).dm, 
                    ((ipi_d_t)value).vector);
        vcpu_unblock(targ);
        if (running)
            smp_send_event_check_cpu(targ->processor);
    }
    return;
}


/*
   dir 1: read 0:write
    inst_type 0:integer 1:floating point
 */
#define SL_INTEGER  0        // store/load interger
#define SL_FLOATING    1       // store/load floating

void emulate_io_inst(VCPU *vcpu, u64 padr, u64 ma)
{
    REGS *regs;
    IA64_BUNDLE bundle;
    int slot, dir=0, inst_type;
    size_t size;
    u64 data, post_update, slot1a, slot1b, temp;
    INST64 inst;
    regs=vcpu_regs(vcpu);
    if (IA64_RETRY == __vmx_get_domain_bundle(regs->cr_iip, &bundle)) {
        /* if fetch code fail, return and try again */
        return;
    }
    slot = ((struct ia64_psr *)&(regs->cr_ipsr))->ri;
    if (!slot) inst.inst = bundle.slot0;
    else if (slot == 1){
        slot1a=bundle.slot1a;
        slot1b=bundle.slot1b;
        inst.inst =slot1a + (slot1b<<18);
    }
    else if (slot == 2) inst.inst = bundle.slot2;


    // Integer Load/Store
    if(inst.M1.major==4&&inst.M1.m==0&&inst.M1.x==0){
        inst_type = SL_INTEGER;  //
        size=(inst.M1.x6&0x3);
        if((inst.M1.x6>>2)>0xb){      // write
            dir=IOREQ_WRITE;     //write
            vcpu_get_gr_nat(vcpu,inst.M4.r2,&data);
        }else if((inst.M1.x6>>2)<0xb){   //  read
            dir=IOREQ_READ;
        }
    }
    // Integer Load + Reg update
    else if(inst.M2.major==4&&inst.M2.m==1&&inst.M2.x==0){
        inst_type = SL_INTEGER;
        dir = IOREQ_READ;     //write
        size = (inst.M2.x6&0x3);
        vcpu_get_gr_nat(vcpu,inst.M2.r3,&temp);
        vcpu_get_gr_nat(vcpu,inst.M2.r2,&post_update);
        temp += post_update;
        vcpu_set_gr(vcpu,inst.M2.r3,temp,0);
    }
    // Integer Load/Store + Imm update
    else if(inst.M3.major==5){
        inst_type = SL_INTEGER;  //
        size=(inst.M3.x6&0x3);
        if((inst.M5.x6>>2)>0xb){      // write
            dir=IOREQ_WRITE;     //write
            vcpu_get_gr_nat(vcpu,inst.M5.r2,&data);
            vcpu_get_gr_nat(vcpu,inst.M5.r3,&temp);
            post_update = (inst.M5.i<<7)+inst.M5.imm7;
            if(inst.M5.s)
                temp -= post_update;
            else
                temp += post_update;
            vcpu_set_gr(vcpu,inst.M5.r3,temp,0);

        }else if((inst.M3.x6>>2)<0xb){   //  read
            dir=IOREQ_READ;
            vcpu_get_gr_nat(vcpu,inst.M3.r3,&temp);
            post_update = (inst.M3.i<<7)+inst.M3.imm7;
            if(inst.M3.s)
                temp -= post_update;
            else
                temp += post_update;
            vcpu_set_gr(vcpu,inst.M3.r3,temp,0);

        }
    }
    // Floating-point spill
    else if (inst.M9.major == 6 && inst.M9.x6 == 0x3B &&
             inst.M9.m == 0 && inst.M9.x == 0) {
        struct ia64_fpreg v;

        inst_type = SL_FLOATING;
        dir = IOREQ_WRITE;
        vcpu_get_fpreg(vcpu, inst.M9.f2, &v);
        /* Write high word.
           FIXME: this is a kludge!  */
        v.u.bits[1] &= 0x3ffff;
        mmio_access(vcpu, padr + 8, &v.u.bits[1], 8, ma, IOREQ_WRITE);
        data = v.u.bits[0];
        size = 3;
    }
    // Floating-point spill + Imm update
    else if(inst.M10.major==7&&inst.M10.x6==0x3B){
        struct ia64_fpreg v;
	inst_type=SL_FLOATING;
	dir=IOREQ_WRITE;
	vcpu_get_fpreg(vcpu,inst.M10.f2,&v);
	vcpu_get_gr_nat(vcpu,inst.M10.r3,&temp);
	post_update = (inst.M10.i<<7)+inst.M10.imm7;
	if(inst.M10.s)
            temp -= post_update;
	else
            temp += post_update;
	vcpu_set_gr(vcpu,inst.M10.r3,temp,0);

	/* Write high word.
	   FIXME: this is a kludge!  */
	v.u.bits[1] &= 0x3ffff;
	mmio_access(vcpu, padr + 8, &v.u.bits[1], 8, ma, IOREQ_WRITE);
	data = v.u.bits[0];
	size = 3;
    }
    // Floating-point stf8 + Imm update
    else if(inst.M10.major==7&&inst.M10.x6==0x31){
        struct ia64_fpreg v;
	inst_type=SL_FLOATING;
	dir=IOREQ_WRITE;
	size=3;
	vcpu_get_fpreg(vcpu,inst.M10.f2,&v);
	data = v.u.bits[0]; /* Significand.  */
	vcpu_get_gr_nat(vcpu,inst.M10.r3,&temp);
	post_update = (inst.M10.i<<7)+inst.M10.imm7;
	if(inst.M10.s)
            temp -= post_update;
	else
            temp += post_update;
	vcpu_set_gr(vcpu,inst.M10.r3,temp,0);
    }
//    else if(inst.M6.major==6&&inst.M6.m==0&&inst.M6.x==0&&inst.M6.x6==3){
//        inst_type=SL_FLOATING;  //fp
//        dir=IOREQ_READ;
//        size=3;     //ldfd
//    }
    //  lfetch - do not perform accesses.
    else if(inst.M15.major==7&&inst.M15.x6>=0x2c&&inst.M15.x6<=0x2f){
	vcpu_get_gr_nat(vcpu,inst.M15.r3,&temp);
	post_update = (inst.M15.i<<7)+inst.M15.imm7;
	if(inst.M15.s)
            temp -= post_update;
	else
            temp += post_update;
	vcpu_set_gr(vcpu,inst.M15.r3,temp,0);

	vmx_vcpu_increment_iip(vcpu);
	return;
    }
    // Floating-point Load Pair + Imm ldfp8 M12
    else if(inst.M12.major==6&&inst.M12.m==1&&inst.M12.x==1&&inst.M12.x6==1){
        struct ia64_fpreg v;
        inst_type=SL_FLOATING;
        dir = IOREQ_READ;
        size = 8;     //ldfd
        mmio_access(vcpu, padr, &data, size, ma, dir);
        v.u.bits[0]=data;
        v.u.bits[1]=0x1003E;
        vcpu_set_fpreg(vcpu,inst.M12.f1,&v);
        padr += 8;
        mmio_access(vcpu, padr, &data, size, ma, dir);
        v.u.bits[0]=data;
        v.u.bits[1]=0x1003E;
        vcpu_set_fpreg(vcpu,inst.M12.f2,&v);
        padr += 8;
        vcpu_set_gr(vcpu,inst.M12.r3,padr,0);
        vmx_vcpu_increment_iip(vcpu);
        return;
    }					
    else{
        panic_domain
	  (NULL,"This memory access instr can't be emulated: %lx pc=%lx\n ",
	   inst.inst, regs->cr_iip);
    }

    size = 1 << size;
    if(dir==IOREQ_WRITE){
        mmio_access(vcpu, padr, &data, size, ma, dir);
    }else{
        mmio_access(vcpu, padr, &data, size, ma, dir);
        if(inst_type==SL_INTEGER){       //gp
            vcpu_set_gr(vcpu,inst.M1.r1,data,0);
        }else{
            panic_domain(NULL, "Don't support ldfd now !");
/*            switch(inst.M6.f1){

            case 6:
                regs->f6=(struct ia64_fpreg)data;
            case 7:
                regs->f7=(struct ia64_fpreg)data;
            case 8:
                regs->f8=(struct ia64_fpreg)data;
            case 9:
                regs->f9=(struct ia64_fpreg)data;
            case 10:
                regs->f10=(struct ia64_fpreg)data;
            case 11:
                regs->f11=(struct ia64_fpreg)data;
            default :
                ia64_ldfs(inst.M6.f1,&data);
            }
*/
        }
    }
    vmx_vcpu_increment_iip(vcpu);
}