/* * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #include "kernel/register.h" #include "kernel/celltypes.h" #include "kernel/rtlil.h" #include "kernel/log.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct SynthPass : public ScriptPass { SynthPass() : ScriptPass("synth", "generic synthesis script") { } void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" synth [options]\n"); log("\n"); log("This command runs the default synthesis script. This command does not operate\n"); log("on partly selected designs.\n"); log("\n"); log(" -top \n"); log(" use the specified module as top module (default='top')\n"); log("\n"); log(" -auto-top\n"); log(" automatically determine the top of the design hierarchy\n"); log("\n"); log(" -flatten\n"); log(" flatten the design before synthesis. this will pass '-auto-top' to\n"); log(" 'hierarchy' if no top module is specified.\n"); log("\n"); log(" -encfile \n"); log(" passed to 'fsm_recode' via 'fsm'\n"); log("\n"); log(" -lut \n"); log(" perform synthesis for a k-LUT architecture.\n"); log("\n"); log(" -nofsm\n"); log(" do not run FSM optimization\n"); log("\n"); log(" -noabc\n"); log(" do not run abc (as if yosys was compiled without ABC support)\n"); log("\n"); log(" -noalumacc\n"); log(" do not run 'alumacc' pass. i.e. keep arithmetic operators in\n"); log(" their direct form ($add, $sub, etc.).\n"); log("\n"); log(" -nordff\n"); log(" passed to 'memory'. prohibits merging of FFs into memory read ports\n"); log("\n"); log(" -noshare\n"); log(" do not run SAT-based resource sharing\n"); log("\n"); log(" -run [:]\n"); log(" only run the commands between the labels (see below). an empty\n"); log(" from label is synonymous to 'begin', and empty to label is\n"); log(" synonymous to the end of the command list.\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } string top_module, fsm_opts, memory_opts; bool autotop, flatten, noalumacc, nofsm, noabc, noshare; int lut; void clear_flags() YS_OVERRIDE { top_module.clear(); fsm_opts.clear(); memory_opts.clear(); autotop = false; flatten = false; lut = 0; noalumacc = false; nofsm = false; noabc = false; noshare = false; } void execute(std::vector args, RTLIL::Design *desi

from countershape import Page

pages = [
     Page("testing.html", "Testing"),
     Page("architecture.html", "Architecture"),
     Page("sslkeylogfile.html", "TLS Master Secrets"),
#    Page("addingviews.html", "Writing Content Views"),
]