aboutsummaryrefslogtreecommitdiffstats
path: root/web/src/js/__tests__/components/EventLogSpec.js
blob: 8510de55722d364cb0457cfb99f27ba023aa92ea (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
jest.mock('../../components/EventLog/EventList')

import React from 'react'
import renderer from 'react-test-renderer'
import TestUtils from 'react-dom/test-utils'
import EventLog, { PureEventLog } from '../../components/EventLog'
import { Provider } from 'react-redux'
import { TStore } from '../ducks/tutils'

window.addEventListener = jest.fn()
window.removeEventListener = jest.fn()

describe('EventLog Component', () => {
    let store = TStore(),
        provider = renderer.create(
        <Provider store={store}>
            <EventLog/>
        </Provider>),
        tree = provider.toJSON()

    it('should connect to state and render correctly', () => {
        expect(tree).toMatchSnapshot()
    })

    it('should handle toggleFilter', () => {
        let debugToggleButton = tree.children[0].children[1].children[0]
        debugToggleButton.props.onClick()
    })

    provider = TestUtils.renderIntoDocument(
        <Provider store={store}><EventLog/></Provider>)
    let eventLog = TestUtils.findRenderedComponentWithType(provider, PureEventLog),
        mockEvent = { preventDefault: jest.fn() }

    it('should handle DragStart', () => {
        eventLog.onDragStart(mockEvent)
        expect(mockEvent.preventDefault).toBeCalled()
        expect(window.addEventListener).toBeCalledWith('mousemove', eventLog.onDragMove)
        expect(window.addEventListener).toBeCalledWith('mouseup', eventLog.onDragStop)
        expect(window.addEventListener).toBeCalledWith('dragend', eventLog.onDragStop)
        mockEvent.preventDefault.mockClear()
    })

    it('should handle DragMove', () => {
        eventLog.onDragMove(mockEvent)
        expect(mockEvent.preventDefault).toBeCalled()
        mockEvent.preventDefault.mockClear()
    })

    console.error = jest.fn() // silent the error.
    it('should handle DragStop', () => {
        eventLog.onDragStop(mockEvent)
        expect(mockEvent.preventDefault).toBeCalled()
        expect(window.removeEventListener).toBeCalledWith('mousemove', eventLog.onDragMove)
    })

})
} ``` **Invariant 3:** ``` if (!ctx->checkPipAvail(pip)) { WireId w = getConflictingPipWire(pip); if (w != WireId()) { ctx->unbindWire(w); assert(ctx->checkPipAvail(pip)); } } ``` **Invariant 4:** ``` if (!ctx->checkPipAvail(pip)) { NetInfo *n = getConflictingPipNet(pip); if (n != nullptr) { for (auto &it : n->wires) ctx->unbindWire(it.first); assert(ctx->checkPipAvail(pip)); } } ``` **Invariant 5:** ``` if (ctx->checkWireAvail(wire)) { // bind is guaranteed to succeed ctx->bindWire(wire, net, strength); } ``` **Invariant 6:** ``` if (ctx->checkPipAvail(pip) && ctx->checkWireAvail(ctx->getPipDstWire(pip))) { // bind is guaranteed to succeed ctx->bindPip(pip, net, strength); } ``` Nextpnr and other tools ----------------------- ### Which toolchain should I use and why? * If you wish to do new **research** into FPGA architectures, or other similar topics, we suggest you look at using [Verilog to Routing](https://verilogtorouting.org). If you want to use nextpnr, you might also be able to use the [Generic Arch](generic.md). * If you are developing FPGA code in **Verilog** for a **Lattice iCE40** and need an open source toolchain, we suggest you use [Yosys](http://www.clifford.at/yosys/) and nextpnr. * If you are developing FPGA code in **Verilog** for a **Lattice iCE40** with Yosys and the **existing arachne-pnr toolchain**, we suggest you start thinking about migrating to nextpnr. * If you are developing Verilog FPGA code targeted at the Lattice ECP5 and need an open source toolchain, there is also stable ECP5 support in Yosys and nextpnr. * If you are developing FPGA code in **VHDL** you may wish to look at the [ghdlsynth-beta](https://github.com/tgingold/ghdlsynth-beta) experimental VHDL frontend for Yosys. ### Why didn't you just improve [arachne-pnr](https://github.com/cseed/arachne-pnr)? [arachne-pnr](https://github.com/cseed/arachne-pnr) was originally developed as part of [Project IceStorm](http://www.clifford.at/icestorm/) to demonstrate it was possible to create an open source place and route tool for the iCE40 FPGAs that actually produced valid bitstreams. For its original purpose, it has served the community extremely well. However, it was never designed to support multiple different FPGA families, nor more complicated timing driven placement and routing used by most commercial place and route tools. It felt like extending arachne-pnr was not going to be the best path forward, so it was decided to build nextpnr as replacement. ### arachne-pnr does X better! If you have a use case which prevents you from switching to nextpnr from arachne, we want to hear about it! Please create an issue and we will do our best to solve the problem! We want nextpnr to be a suitable replacement for anyone who is currently a user of arachne-pnr, and it is important to bear in mind that arachne-pnr is no longer in active development. ### Why are you not just contributing to [Verilog to Routing](https://verilogtorouting.org)? We believe that [Verilog to Routing](https://verilogtorouting.org) is a great toolchain and many of the nextpnr developers have made (and continue to make) contributions to the project. VtR is an extremely flexible toolchain but focuses on research around FPGA architecture and algorithm development. If your goal is research, then we very much encourage you to look into VtR further! nextpnr takes a different approach by focusing on users developing FPGA code for current FPGAs. We also believe that support for real architectures will enable interesting new research. nextpnr (like all place and route tools) depends heavily on research groups like the VtR developers to investigate and push forward FPGA placement and routing algorithms in new and exciting ways. #### What is VPR? VPR is the "place and route" tool from Verilog To Routing. It has a similar role in an FPGA development flow as nextpnr. ### What about [SymbiFlow](http://symbiflow.github.io)? For the moment [SymbiFlow](http://github.com/SymbiFlow) is concentrating on extending VPR to work with real world architectures. nextpnr may or may not become a part of SymbiFlow in the future. ### What is [Project Trellis](https://github.com/SymbiFlow/prjtrellis)? [Project Trellis](https://github.com/SymbiFlow/prjtrellis) is the effort to document the bitstream format for the Lattice ECP5 series of FPGAs. It also includes tools for ECP5 bitstream generation. Project Trellis is used by nextpnr to build the ECP5 chip database and enable support for creation of bitstreams for these parts. ### What is [Project X-Ray](https://github.com/SymbiFlow/prjxray)? [Project X-Ray](https://github.com/SymbiFlow/prjxray) is the effort to document the bitstream format for the Xilinx Series 7 series of FPGAs. It also includes tooling around bitstream generation for these parts. While upstream nextpnr currently does **not** support these Xilinx parts, we expect it might soon be using Project X-Ray in a similar manner to Project Trellis. ### What is [Project IceStorm](http://www.clifford.at/icestorm/)? [Project IceStorm](http://www.clifford.at/icestorm/) is both a project to document the bitstream for the Lattice iCE40 series of parts **and** a full flow including Yosys and arachne-pnr for converting Verilog into a bitstream for these parts. As the open source community now has support for multiple different FPGA parts, in the nextpnr documentation we generally use Project IceStorm to mean the database and tools that fulfil the same role as Project Trellis or Project X-Ray.