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* c4 hdmiJames McKenzie2025-04-282-0/+544
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* c4 hdmiJames McKenzie2025-04-288-209/+125
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* tidyJames McKenzie2025-04-283-44/+44
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* tidyJames McKenzie2025-04-282-37/+37
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* cyclone4 first stepsJames McKenzie2025-04-2815-40/+743
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* move vram to moduleJames McKenzie2025-04-285-2/+38
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* tidyJames McKenzie2025-04-288-187/+188
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* tidyJames McKenzie2025-04-289-228/+255
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* finished input stageJames McKenzie2025-04-272-0/+941
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* finished input stageJames McKenzie2025-04-279-675/+137
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* tidyJames McKenzie2025-04-278-455/+457
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* meets timingJames McKenzie2025-04-274-102/+74
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* note quite workingJames McKenzie2025-04-273-25/+75
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* note quite workingJames McKenzie2025-04-2710-96/+628
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* after tidyJames McKenzie2025-04-2610-749/+563
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* before tidyJames McKenzie2025-04-2614-109/+1481
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* first cut at spartan 6 fpgaJames McKenzie2025-04-2615-763/+707
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* fix aux channel polarityJames McKenzie2025-04-2520-2132/+2598
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* add noddy cyclone IV fpga designJames McKenzie2025-04-2015-0/+1743
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* fishJames McKenzie2025-04-18246-0/+519681
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* tidy up after rebaseJames McKenzie2025-04-181-0/+2
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* fishJames McKenzie2025-04-181-0/+66607
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* add vertical timingsroot2025-04-1814-36/+131185
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* fishJames McKenzie2025-04-161-0/+0
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* fishJames McKenzie2025-04-1639-0/+0
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* add lcsc part numbersJames McKenzie2025-04-162-4/+121
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* schematicsJames McKenzie2025-04-163-0/+0
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* fishroot2025-04-165-0/+3
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* add submoduleJames McKenzie2025-04-162-0/+4
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* tidy upJames McKenzie2025-04-1558-0/+207425
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-20 06:00:52 +0000