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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.all;
entity hp_lcd_driver is
generic (input_video_width : natural := 2;
video_width : natural := 2;
addr_width : natural := 18;
phase_slip : natural := 320;
i_clk_multiple : natural := 4;
use_pclk : natural := 0;
target : string := "artix7");
port (clk_50m : in std_logic;
sys_rst_n : in std_logic;
video : in std_logic_vector(input_video_width -1 downto 0);
hsync_in : in std_logic;
vsync_in : in std_logic;
pclk_in : in std_logic;
r_out : out std_logic;
b_out : out std_logic;
g_out : out std_logic;
hsync_out : out std_logic;
vsync_out : out std_logic;
hdmi_c_p : out std_logic;
hdmi_c_n : out std_logic;
hdmi_r_p : out std_logic;
hdmi_r_n : out std_logic;
hdmi_g_p : out std_logic;
hdmi_g_n : out std_logic;
hdmi_b_p : out std_logic;
hdmi_b_n : out std_logic;
hdmi_vcc : out std_logic;
i_clk_out : out std_logic;
led : out std_logic);
end hp_lcd_driver;
architecture Behavioral of hp_lcd_driver is
begin
common_i : entity work.common
generic map (
input_video_width => input_video_width,
video_width => video_width,
addr_width => addr_width,
phase_slip => phase_slip,
i_clk_multiple => i_clk_multiple,
use_pclk => use_pclk,
target => target)
port map (clk_50m => clk_50m,
sys_rst_n => sys_rst_n,
video => video,
hsync_in => hsync_in,
vsync_in => vsync_in,
pclk_in => pclk_in,
r_out => r_out,
b_out => b_out,
g_out => g_out,
hsync_out => hsync_out,
vsync_out => vsync_out,
hdmi_c_p => hdmi_c_p,
hdmi_c_n => hdmi_c_n,
hdmi_r_p => hdmi_r_p,
hdmi_r_n => hdmi_r_n,
hdmi_g_p => hdmi_g_p,
hdmi_g_n => hdmi_g_n,
hdmi_b_p => hdmi_b_p,
hdmi_b_n => hdmi_b_n,
hdmi_vcc => hdmi_vcc,
i_clk_out => i_clk_out,
led => led,
video_out_clk => open,
video_out_index => open,
video_out_data => open,
video_out_valid => open
);
end Behavioral;
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