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path: root/src/aig/gia/giaMini.c
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* Improvements to MiniAIG.Alan Mishchenko2022-05-181-1/+44
* Removing equivalence classes when they are not properly refined.Alan Mishchenko2022-04-281-0/+3
* New API for external calls.Alan Mishchenko2021-10-261-0/+16
* Improving MiniAIG and name manager.Alan Mishchenko2021-09-161-11/+15
* Further debugging of MiniLUT APIs.Alan Mishchenko2021-09-161-1/+72
* Bug fix in MiniLUT code.Alan Mishchenko2021-09-131-1/+1
* Additional MiniLUT API.Alan Mishchenko2021-09-031-0/+17
* New ways of reading MiniAIG.Alan Mishchenko2020-07-291-1/+1
* New ways of reading MiniAIG.Alan Mishchenko2020-07-291-0/+268
* Corner-case bug in MiniLUT computation.Alan Mishchenko2020-04-021-0/+1
* Adding switch &w -n to modify the comment section of the AIGER file written.Alan Mishchenko2018-11-211-3/+3
* Procedures to verify equivalence classes.Alan Mishchenko2018-11-111-1/+139
* Procedure to return seq equivalences.Alan Mishchenko2018-07-221-0/+68
* Making sure duplicated inverters are not created.Alan Mishchenko2018-04-111-3/+9
* Extending MiniLUT to return attributes.Alan Mishchenko2018-02-111-0/+19
* Adding API to dump MiniAIG into a Verilog file and other small changes.Alan Mishchenko2017-10-221-0/+1
* Compiler warnings.Alan Mishchenko2017-07-221-1/+1
* Bug fix in MiniLUT APIs.Alan Mishchenko2017-07-121-1/+31
* Making MiniLUT work for more than 6 inputs.Alan Mishchenko2017-07-081-17/+38
* Synchronizing various data-structures.Alan Mishchenko2017-07-041-10/+124
* Corner-case bug in MiniLUT.Alan Mishchenko2017-01-251-0/+1
* Dealing wit COs driven by inverters in MiniLUT.Alan Mishchenko2017-01-061-2/+38
* Adding support for minimalistic representation of LUT mapping.Alan Mishchenko2016-12-051-1/+1
* Adding support for minimalistic representation of LUT mapping.Alan Mishchenko2016-12-051-0/+182
* Reading/writing MiniAIG and several minor changes.Alan Mishchenko2013-05-031-0/+2
* Reading/writing MiniAIG and several minor changes.Alan Mishchenko2013-05-031-0/+187
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