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* Merge remote-tracking branch 'upstream/master' into yosys-experimentalMiodrag Milanovic2022-11-095-2/+38
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| * Adding comment about dup cell name.Alan Mishchenko2022-10-111-0/+2
| * Updating features of &if mapper.Alan Mishchenko2022-10-094-2/+36
* | Additional fix for large liberty filesMiodrag Milanovic2022-09-081-26/+26
* | Support using large liberty filesMiodrag Milanovic2022-09-071-5/+5
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* Experiments with the mapper.Alan Mishchenko2022-06-235-0/+73
* Adding switch to dsd_match to skip small functions.Alan Mishchenko2022-05-182-5/+5
* Merge pull request #145 from QuantamHD/fix_internal_pinsalanminko2022-04-041-1/+5
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| * Fixes internal pin parsing error in ASAP7 liberty file.QuantamHD2021-12-201-1/+5
* | Suggested changes for the case when the file begings with a new line.Alan Mishchenko2022-03-292-53/+74
* | Suggested bug fixes in the old code.Alan Mishchenko2022-01-211-4/+3
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* Changing declaration of Vec_Ptr_t sorting function to satisfy some compilers.Alan Mishchenko2021-09-262-2/+2
* Two rare corner-case bugs in &if mapper.Alan Mishchenko2021-09-261-1/+1
* Experiments with CEC.Alan Mishchenko2021-07-101-2/+2
* Experiments with MUX decomposition.Alan Mishchenko2021-07-081-4/+4
* Updating LUT synthesis code.Alan Mishchenko2021-05-261-0/+1
* Several changes for standard mapping.Alan Mishchenko2021-04-281-2/+13
* Updating the mapper when user-specific matching is used.Alan Mishchenko2021-01-091-0/+12
* Rare bug fix in mapping with choices.Alan Mishchenko2020-10-291-1/+2
* Compiler warnings.Alan Mishchenko2020-05-031-1/+0
* Adding dumping of genlib library in Verilog.Alan Mishchenko2020-05-032-30/+30
* Adding dumping of genlib library in Verilog.Alan Mishchenko2020-05-031-1/+1
* Adding dumping of genlib library in Verilog.Alan Mishchenko2020-05-034-7/+110
* Adding dynamic memory alloc for the buffer in Liberty file reader.Alan Mishchenko2020-01-111-3/+9
* Making sure arrival time of constant node is -infinity.Alan Mishchenko2020-01-021-0/+2
* Adding limit on the depth of recursion when counting exact area in 'amap'.Alan Mishchenko2019-10-263-1/+62
* Small bug in the unused code.Alan Mishchenko2019-10-041-1/+1
* Adding switch to &if to consider special type of 6-input cuts.Alan Mishchenko2019-09-264-0/+84
* Making &mfs work with boxes larger than 6 inputs. Adding option &if -w to pri...Alan Mishchenko2019-09-191-0/+1
* Fixing some update gcc.Alan Mishchenko2019-07-241-1/+1
* Adding support for user-specified wire delays in &if.Alan Mishchenko2019-05-291-1/+1
* Prevent assertions from firing for deep logic networks.Alan Mishchenko2019-03-201-4/+4
* Fixing some warnings by adding cast from 'int' to 'size_t' in memset, memcpy,...Alan Mishchenko2019-03-0517-26/+26
* Fixing some warnings with -Wconversion.Alan Mishchenko2019-03-051-2/+2
* Fixing float overflow during edge-flow computation in 'if' mapper (change to ...Alan Mishchenko2018-12-121-0/+8
* Fixing float overflow during edge-flow computation in 'if' mapper.Alan Mishchenko2018-12-121-3/+7
* Adding switch &w -n to modify the comment section of the AIGER file written.Alan Mishchenko2018-11-211-2/+2
* Skip cells in Liberty files which have dont_use attribute.Alan Mishchenko2018-10-182-3/+56
* Suggested bug fix in 'amap'.Alan Mishchenko2018-09-131-0/+3
* Adding parameters and improvements to %blast.Alan Mishchenko2018-02-282-0/+8
* Compilation problem with pow().Alan Mishchenko2018-02-191-2/+2
* Value of properties can be expression.Staf Verhaegen2018-01-031-0/+12
* Adding API to dump MiniAIG into a Verilog file and other small changes.Alan Mishchenko2017-10-222-0/+3
* Fix typo on the message reporting max output load.Alan Mishchenko2017-10-111-1/+1
* Updates and bug fixes.Alan Mishchenko2017-10-043-11/+19
* Maintenance and updates.Alan Mishchenko2017-09-245-3/+57
* Maintenance and updates.Alan Mishchenko2017-09-202-3/+7
* Maintenance and updates.Alan Mishchenko2017-09-184-0/+56
* Compiler warnings.Alan Mishchenko2017-07-226-8/+8
* Synchronizing various data-structures.Alan Mishchenko2017-07-042-7/+162
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