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* Restructuring gate-sizing code trying to separate timing analysis.Alan Mishchenko2013-07-2113-298/+580
* New technology mapper.Alan Mishchenko2013-07-216-20/+25
* Improvements to post-mapping re-sizing.Alan Mishchenko2013-07-217-131/+159
* Adding support for input slew and output capacitance to timer and gate-sizer.Alan Mishchenko2013-07-214-3/+97
* Improvements to the SCL package.Alan Mishchenko2013-07-206-159/+52
* Added command 'dnsize' to complement command 'upsize'.Alan Mishchenko2013-07-208-31/+730
* Small changes to the printout in timing analysis.Alan Mishchenko2013-07-193-3/+5
* Temprary changes.Alan Mishchenko2013-07-181-1/+50
* New technology mapper.Alan Mishchenko2013-07-181-1/+1
* New technology mapper.Alan Mishchenko2013-07-183-53/+32
* Temprary changes.Alan Mishchenko2013-07-181-0/+49
* New technology mapper.Alan Mishchenko2013-07-184-82/+41
* New technology mapper.Alan Mishchenko2013-07-183-46/+93
* New technology mapper.Alan Mishchenko2013-07-175-24/+46
* New technology mapper.Alan Mishchenko2013-07-171-1/+1
* New technology mapper.Alan Mishchenko2013-07-171-1/+1
* New technology mapper.Alan Mishchenko2013-07-178-25/+356
* Commenting out assertion related to choices in 'if'.Alan Mishchenko2013-07-161-1/+1
* New technology mapper.Alan Mishchenko2013-07-156-19/+15
* New technology mapper.Alan Mishchenko2013-07-143-4/+10
* New technology mapper.Alan Mishchenko2013-07-146-216/+225
* New technology mapper.Alan Mishchenko2013-07-149-694/+934
* New technology mapper.Alan Mishchenko2013-07-139-106/+1086
* New technology mapper.Alan Mishchenko2013-07-137-9/+79
* New technology mapper.Alan Mishchenko2013-07-131-1/+1
* New technology mapper.Alan Mishchenko2013-07-134-66/+71
* New technology mapper.Alan Mishchenko2013-07-131-0/+1
* New technology mapper.Alan Mishchenko2013-07-131-2/+2
* New technology mapper.Alan Mishchenko2013-07-136-235/+277
* New technology mapper.Alan Mishchenko2013-07-127-134/+295
* Compiler warnings.Alan Mishchenko2013-07-121-8/+7
* New technology mapper.Alan Mishchenko2013-07-1214-6/+2496
* Precomputing DSD functions.Alan Mishchenko2013-07-111-10/+73
* Precomputing DSD functions.Alan Mishchenko2013-07-111-31/+423
* Saving delay information after mapping.Alan Mishchenko2013-06-262-0/+2
* Improving integration of the 'if' mapper with GIA.Alan Mishchenko2013-06-251-0/+1
* New features to debug an test tech-mapping with choices.Alan Mishchenko2013-06-242-0/+602
* Bug fix in gate sizing.Alan Mishchenko2013-06-161-1/+1
* New DSD detection code.Alan Mishchenko2013-05-301-0/+425
* Adding a wrapper around clock() for more accurate time counting in ABC.Alan Mishchenko2013-05-2726-149/+149
* New MFS package.Alan Mishchenko2013-05-261-1/+1
* New MFS package.Alan Mishchenko2013-05-241-4/+4
* Changing the queue to work in the same the array of costs is realloced.Alan Mishchenko2013-05-051-2/+2
* Compiler warnings.Alan Mishchenko2013-03-301-1/+2
* Compiler warnings.Alan Mishchenko2013-03-301-1/+1
* Modified SCL gate library to read/write gate formula.Alan Mishchenko2013-03-266-15/+159
* Integrating box library.Alan Mishchenko2013-03-082-0/+33
* Improvements to the hierarchy/timing manager.Alan Mishchenko2013-03-053-11/+135
* Improvements to the hierarchy/timing manager.Alan Mishchenko2013-03-056-15/+19
* User-controlable SAT sweeper and other small changes.Alan Mishchenko2013-02-271-1/+0