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* silence clang errors when compiling as C++Baruch Sterin2015-11-051-1/+1
* Bug fix in constructing internal choices by 'amap'.Alan Mishchenko2015-11-041-1/+1
* Experiments with precomputation and matching.Alan Mishchenko2015-10-272-0/+2
* Changes for delay-oriented computation.Alan Mishchenko2015-10-261-1/+1
* Extending library handling to 8 inputs.Alan Mishchenko2015-10-253-2/+62
* Adding switch in 'print_genlib' and 'write_genlib' to print area-min gates only.Alan Mishchenko2015-10-233-16/+38
* Changes for delay-oriented computation.Alan Mishchenko2015-10-232-2/+4
* Compiler warnings.Alan Mishchenko2015-10-211-2/+2
* Moving BDD-based threshold function detection to the BDD part of the code.Alan Mishchenko2015-10-162-0/+9
* Experiments with precomputation and matching.Alan Mishchenko2015-10-152-0/+2
* Experiments with precomputation and matching.Alan Mishchenko2015-10-124-15/+31
* Two fixes in 'dsd_filter'.Alan Mishchenko2015-10-071-1/+1
* Bug fix in 'if -g' (incorrect use of a macro).Alan Mishchenko2015-10-071-3/+3
* Improvements to Scl_Lib/SC_Cell data-structure.Alan Mishchenko2015-09-246-230/+211
* Several bug-fixed related to synthesis, library handling, and timimg info.Alan Mishchenko2015-09-231-2/+4
* Threshold logic checking code by Augusto Neutzling and Jody Matos.Alan Mishchenko2015-09-231-3/+6
* New constraint manager and memory reporting 'ps'.Alan Mishchenko2015-09-085-16/+425
* Updating Mio to use int instead of float.Alan Mishchenko2015-08-312-2/+192
* Alternative way to bit-blast a divisor.Alan Mishchenko2015-08-291-1/+1
* Important bug fixes in standard-cell library handling and mapper &nf.Alan Mishchenko2015-08-284-14/+34
* Changes to be able to compile ABC without CUDD.Alan Mishchenko2015-08-242-1/+3
* New switch in 'read_lib' to replace gate/pin names by short strings.Alan Mishchenko2015-08-241-5/+44
* New switch in 'read_lib' to replace gate/pin names by short strings.Alan Mishchenko2015-08-243-2/+105
* Experiments with mapping plus small changes.Alan Mishchenko2015-08-233-3/+10
* Small changes to enable collecting results using &ps -D file.Alan Mishchenko2015-07-092-0/+2
* Bug fix in programmable cell parser and minor tuning.Alan Mishchenko2015-07-081-1/+2
* C++ compiler typecast problem.Alan Mishchenko2015-07-081-1/+1
* Add fix to Liberty parser to skip extra semicolon.Alan Mishchenko2015-07-061-0/+5
* Undo recent assert.Alan Mishchenko2015-06-271-2/+2
* Potential performance bug in the mapper.Alan Mishchenko2015-06-271-1/+1
* Supporting AND-gate cuts in 'if' and '&if'Alan Mishchenko2015-06-213-6/+27
* Bug fix in 'dsd_tune' when processing cells with 0-input LUTs.Alan Mishchenko2015-05-151-2/+7
* Making sure 0-input LUTs are supported by the DSD matching code.Alan Mishchenko2015-05-141-5/+5
* Improving the criteria to select representative gates in 'map' with floating-...Alan Mishchenko2015-04-251-47/+60
* Adding switch 'map -f' to not use large gates for high-fanout nodes (disabled...Alan Mishchenko2015-04-244-2/+5
* Adding platform-independent (alphabetic) way of sorting Genlib gates and sele...Alan Mishchenko2015-04-172-20/+56
* Adding APIs to retrieve NOR/OR gates from the library.Alan Mishchenko2015-04-144-4/+15
* Getting default AND-node delay from Genlib library.Alan Mishchenko2015-04-062-0/+2
* Support for representing programmable cell configuration data (bug fix).Alan Mishchenko2015-03-091-1/+4
* Support for representing programmable cell configuration data.Alan Mishchenko2015-03-081-1/+2
* Support for representing programmable cell configuration data.Alan Mishchenko2015-03-083-64/+222
* Experiments with SAT-based cube enumeration.Alan Mishchenko2015-03-051-3/+4
* Corner case bug in wire-cap estimation.Alan Mishchenko2015-02-181-0/+2
* Several improvements to CBA data-structure.Alan Mishchenko2015-02-091-1/+1
* Fixed a typo in variable names.Alan Mishchenko2015-02-075-24/+24
* Improvements and tuning of CBA with buffering/sizing.Alan Mishchenko2015-02-045-28/+77
* Improvements and tuning of CBA.Alan Mishchenko2015-02-011-0/+2
* Major rehash of the CBA code.Alan Mishchenko2015-01-312-0/+21
* New assertions and bug fix in DSD balancing.Alan Mishchenko2015-01-272-8/+11
* Gate sizing with barrier buffers.Alan Mishchenko2014-12-213-1/+52
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