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* Integrated buffering and sizing.Alan Mishchenko2013-08-108-102/+186
* Integrated buffering and sizing.Alan Mishchenko2013-08-101-5/+5
* Bug fix in incremental timing.Alan Mishchenko2013-08-102-12/+18
* Enable wire load estimation in buffering/sizing.Alan Mishchenko2013-08-106-38/+46
* Integrated buffering and sizing.Alan Mishchenko2013-08-093-19/+16
* Integrated buffering and sizing.Alan Mishchenko2013-08-094-21/+19
* Integrated buffering and sizing.Alan Mishchenko2013-08-094-67/+89
* Integrated buffering and sizing.Alan Mishchenko2013-08-094-30/+67
* Improvements to buffering and sizing.Alan Mishchenko2013-08-096-29/+101
* Improvements to buffering and sizing.Alan Mishchenko2013-08-097-85/+242
* Improvements to buffering and sizing.Alan Mishchenko2013-08-093-67/+26
* Improvements to buffering and sizing.Alan Mishchenko2013-08-097-124/+181
* Compiler warnings.Alan Mishchenko2013-08-081-1/+1
* Integrated buffering and sizing.Alan Mishchenko2013-08-0812-99/+683
* Improvements to buffering and sizing.Alan Mishchenko2013-08-072-172/+159
* Improvements to buffering and sizing.Alan Mishchenko2013-08-068-36/+502
* Improvements to buffering and sizing.Alan Mishchenko2013-08-064-18/+288
* Adding new (un)buffering with phase information.Alan Mishchenko2013-08-051-5/+30
* Adding new (un)buffering with phase information.Alan Mishchenko2013-08-053-9/+107
* Adding code to estimate buffer trees.Alan Mishchenko2013-08-057-43/+249
* Change from input slew to input drive strength in the BLIF file.Alan Mishchenko2013-08-045-10/+81
* Adding switch 'buffer -p' to enable buffing of the primary inputs.Alan Mishchenko2013-08-023-9/+16
* Internal parameter tuning.Alan Mishchenko2013-07-311-1/+1
* Parametrizing standard-cell mapper to account for the fanout delay.Alan Mishchenko2013-07-305-10/+47
* Added commands 'maxsize' and 'unbuffer'.Alan Mishchenko2013-07-291-3/+8
* Added commands 'maxsize' and 'unbuffer'.Alan Mishchenko2013-07-293-8/+192
* Compiler warning.Alan Mishchenko2013-07-291-1/+1
* Improved buffering.Alan Mishchenko2013-07-298-333/+334
* Improved gate-sizing.Alan Mishchenko2013-07-297-3/+600
* Tuning standard-cell mapping flow.Alan Mishchenko2013-07-249-65/+112
* Tuning standard-cell mapping flow.Alan Mishchenko2013-07-232-4/+5
* Tuning standard-cell mapping flow.Alan Mishchenko2013-07-231-1/+1
* Tuning standard-cell mapping flow.Alan Mishchenko2013-07-236-171/+246
* Bug fix and warning print.Alan Mishchenko2013-07-222-2/+5
* Generating GENLIB library from SCL.Alan Mishchenko2013-07-228-185/+470
* Restructuring gate-sizing code trying to separate timing analysis.Alan Mishchenko2013-07-2113-298/+580
* New technology mapper.Alan Mishchenko2013-07-216-20/+25
* Improvements to post-mapping re-sizing.Alan Mishchenko2013-07-217-131/+159
* Adding support for input slew and output capacitance to timer and gate-sizer.Alan Mishchenko2013-07-214-3/+97
* Improvements to the SCL package.Alan Mishchenko2013-07-206-159/+52
* Added command 'dnsize' to complement command 'upsize'.Alan Mishchenko2013-07-208-31/+730
* Small changes to the printout in timing analysis.Alan Mishchenko2013-07-193-3/+5
* Temprary changes.Alan Mishchenko2013-07-181-1/+50
* New technology mapper.Alan Mishchenko2013-07-181-1/+1
* New technology mapper.Alan Mishchenko2013-07-183-53/+32
* Temprary changes.Alan Mishchenko2013-07-181-0/+49
* New technology mapper.Alan Mishchenko2013-07-184-82/+41
* New technology mapper.Alan Mishchenko2013-07-183-46/+93
* New technology mapper.Alan Mishchenko2013-07-175-24/+46
* New technology mapper.Alan Mishchenko2013-07-171-1/+1