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| author | Alexander Goncharov <chat@joursoir.net> | 2022-08-17 21:22:27 +0300 |
|---|---|---|
| committer | Anastasia Klimchuk <aklm@chromium.org> | 2022-08-29 03:03:06 +0000 |
| commit | 179e6e14236d297f473612cc121a8f1d88dea03b (patch) | |
| tree | a24da4d96d63338fa80abdc692b3b43edd5ca0ee | |
| parent | 0ba49071005b2d1fe215145deff18d2e8bb178bc (diff) | |
| download | flashrom-179e6e14236d297f473612cc121a8f1d88dea03b.tar.gz flashrom-179e6e14236d297f473612cc121a8f1d88dea03b.tar.bz2 flashrom-179e6e14236d297f473612cc121a8f1d88dea03b.zip | |
it8212: restore ROM BAR decode state explicitly
Instead of using reversible write (rpci_write_long) that relies on
global state, do it manually. Save original PCI config space
register contents to programmer's structure during initialization
and restore it in programmer's shutdown.
TOPIC=reduce_global_pci_state
TEST=builds
Change-Id: I44a4321256d208f7a59e952cd8943b941787fa02
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Ticket: https://ticket.coreboot.org/issues/389
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | it8212.c | 13 |
1 files changed, 11 insertions, 2 deletions
@@ -21,7 +21,9 @@ #include "platform/pci.h" struct it8212_data { + struct pci_dev *dev; uint8_t *bar; + uint32_t decode_access; }; #define PCI_VENDOR_ID_ITE 0x1283 @@ -51,6 +53,11 @@ static uint8_t it8212_chip_readb(const struct flashctx *flash, const chipaddr ad static int it8212_shutdown(void *par_data) { + struct it8212_data *data = par_data; + + /* Restore ROM BAR decode state. */ + pci_write_long(data->dev, PCI_ROM_ADDRESS, data->decode_access); + free(par_data); return 0; } @@ -89,10 +96,12 @@ static int it8212_init(void) msg_perr("Unable to allocate space for PAR master data\n"); return 1; } + data->dev = dev; data->bar = bar; - /* Restore ROM BAR decode state automatically at shutdown. */ - rpci_write_long(dev, PCI_ROM_ADDRESS, io_base_addr | 0x01); + /* Enable ROM BAR decoding. */ + data->decode_access = pci_read_long(dev, PCI_ROM_ADDRESS); + pci_write_long(dev, PCI_ROM_ADDRESS, io_base_addr | 0x01); max_rom_decode.parallel = IT8212_MEMMAP_SIZE; return register_par_master(&par_master_it8212, BUS_PARALLEL, data); |