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author | Edward O'Callaghan <quasisec@google.com> | 2020-12-02 13:17:46 +1100 |
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committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-12-02 23:41:05 +0000 |
commit | 705212dac9961398f552b749bddb0bc113dd2f18 (patch) | |
tree | c26b97f717673ece4db533cdd6870b29893c1437 | |
parent | b1e61bcf9c7bf95aa8afbaa8836f5c893762142a (diff) | |
download | flashrom-705212dac9961398f552b749bddb0bc113dd2f18.tar.gz flashrom-705212dac9961398f552b749bddb0bc113dd2f18.tar.bz2 flashrom-705212dac9961398f552b749bddb0bc113dd2f18.zip |
chipset_enable.c: Validate physmap() return rcrb value
Validate the physical mapping in enable_flash_silvermont().
Change-Id: Icc5a799a06b3f310d9a191fa5eb99b255b20d79d
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/48225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-rw-r--r-- | chipset_enable.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index 5e4a547d..7c98798c 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -996,6 +996,8 @@ static int enable_flash_silvermont(struct pci_dev *dev, const char *name) /* Handle GCS (in RCRB) */ void *rcrb = physmap("BYT RCRB", rcba, 4); + if (rcrb == ERROR_PTR) + return ERROR_FATAL; const enum chipbustype boot_buses = enable_flash_ich_report_gcs(dev, ich_generation, rcrb); physunmap(rcrb, 4); |