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authorNico Huber <nico.h@gmx.de>2022-05-24 15:07:34 +0200
committerNico Huber <nico.h@gmx.de>2022-06-23 14:38:08 +0000
commitd90e2b3e2c37aa63e0dbb4e7359e8043704d815b (patch)
tree0299fa7ae376cd15ea45bf8b2d7729c0dda0d9dd
parent418916428f38e86368c980cc7efdf5c9c615f7cd (diff)
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flashchips,spi25: Replace `.wrea_override` with FEATURE_4BA_EAR_1716
There are two competing sets of instructions to access the extended address register of 4BA SPI chips. Some chips even support both sets. So far, we assumed the 0xc5/0xc8 instructions by default and allowed to override the write instructions with the `.wrea_override` field. This has some disadvantages: * The additional field is easily overlooked. So when adding a new flash chip, one might assume only 0xc5/0xc8 are supported. * We cannot describe flash chips completely that allow both instructions (and some programmers may be picky about which instructions can be used). Therefore, replace the `.wrea_override` field with a feature flag. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: I6d82f24898acd0789203516a7456fd785907bc10 Ticket: https://ticket.coreboot.org/issues/357 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
-rw-r--r--dediprog.c2
-rw-r--r--flashchips.c4
-rw-r--r--include/flash.h23
-rw-r--r--include/spi.h2
-rw-r--r--spi25.c13
5 files changed, 27 insertions, 17 deletions
diff --git a/dediprog.c b/dediprog.c
index 7a7ae3b7..42e0ed92 100644
--- a/dediprog.c
+++ b/dediprog.c
@@ -416,7 +416,7 @@ static int prepare_rw_cmd(
}
}
} else {
- if (flash->chip->feature_bits & FEATURE_4BA_EAR_C5C8) {
+ if (flash->chip->feature_bits & FEATURE_4BA_EAR_ANY) {
if (spi_set_extended_address(flash, start >> 24))
return 1;
} else if (start >> 24) {
diff --git a/flashchips.c b/flashchips.c
index c740d1c8..b45054c4 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -16795,7 +16795,8 @@ const struct flashchip flashchips[] = {
.total_size = 32768,
.page_size = 256,
/* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */
- .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_EAR7,
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP |
+ FEATURE_4BA_NATIVE | FEATURE_4BA_ENTER_EAR7 | FEATURE_4BA_EAR_1716,
.tested = TEST_OK_PREW,
.probe = probe_spi_rdid,
.probe_timing = TIMING_ZERO,
@@ -16829,7 +16830,6 @@ const struct flashchip flashchips[] = {
.write = spi_chip_write_256, /* Multi I/O supported */
.read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
.voltage = {2700, 3600},
- .wrea_override = 0x17,
},
{
diff --git a/include/flash.h b/include/flash.h
index 1f422ef9..449ed9d1 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -129,10 +129,12 @@ enum write_granularity {
#define FEATURE_4BA_EAR_C5C8 (1 << 13) /**< Regular 3-byte operations can be used by writing the most
significant address byte into an extended address register
(using 0xc5/0xc8 instructions). */
-#define FEATURE_4BA_READ (1 << 14) /**< Native 4BA read instruction (0x13) is supported. */
-#define FEATURE_4BA_FAST_READ (1 << 15) /**< Native 4BA fast read instruction (0x0c) is supported. */
-#define FEATURE_4BA_WRITE (1 << 16) /**< Native 4BA byte program (0x12) is supported. */
+#define FEATURE_4BA_EAR_1716 (1 << 14) /**< Like FEATURE_4BA_EAR_C5C8 but with 0x17/0x16 instructions. */
+#define FEATURE_4BA_READ (1 << 15) /**< Native 4BA read instruction (0x13) is supported. */
+#define FEATURE_4BA_FAST_READ (1 << 16) /**< Native 4BA fast read instruction (0x0c) is supported. */
+#define FEATURE_4BA_WRITE (1 << 17) /**< Native 4BA byte program (0x12) is supported. */
/* 4BA Shorthands */
+#define FEATURE_4BA_EAR_ANY (FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_EAR_1716)
#define FEATURE_4BA_NATIVE (FEATURE_4BA_READ | FEATURE_4BA_FAST_READ | FEATURE_4BA_WRITE)
#define FEATURE_4BA (FEATURE_4BA_ENTER | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_NATIVE)
#define FEATURE_4BA_WREN (FEATURE_4BA_ENTER_WREN | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_NATIVE)
@@ -141,13 +143,13 @@ enum write_granularity {
* Most flash chips are erased to ones and programmed to zeros. However, some
* other flash chips, such as the ENE KB9012 internal flash, work the opposite way.
*/
-#define FEATURE_ERASED_ZERO (1 << 17)
-#define FEATURE_NO_ERASE (1 << 18)
+#define FEATURE_ERASED_ZERO (1 << 18)
+#define FEATURE_NO_ERASE (1 << 19)
-#define FEATURE_WRSR_EXT2 (1 << 19)
-#define FEATURE_WRSR2 (1 << 20)
-#define FEATURE_WRSR_EXT3 ((1 << 21) | FEATURE_WRSR_EXT2)
-#define FEATURE_WRSR3 (1 << 22)
+#define FEATURE_WRSR_EXT2 (1 << 20)
+#define FEATURE_WRSR2 (1 << 21)
+#define FEATURE_WRSR_EXT3 ((1 << 22) | FEATURE_WRSR_EXT2)
+#define FEATURE_WRSR3 (1 << 23)
#define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff)
@@ -277,9 +279,6 @@ struct flashchip {
} voltage;
enum write_granularity gran;
- /* SPI specific options (TODO: Make it a union in case other bustypes get specific options.) */
- uint8_t wrea_override; /**< override opcode for write extended address register */
-
struct reg_bit_map {
/* Status register protection bit (SRP) */
struct reg_bit_info srp;
diff --git a/include/spi.h b/include/spi.h
index 05d2239a..9b38cab6 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -175,9 +175,11 @@
/* Write Extended Address Register */
#define JEDEC_WRITE_EXT_ADDR_REG 0xC5
+#define ALT_WRITE_EXT_ADDR_REG_17 0x17
/* Read Extended Address Register */
#define JEDEC_READ_EXT_ADDR_REG 0xC8
+#define ALT_READ_EXT_ADDR_REG_16 0x16
/* Read the memory */
#define JEDEC_READ 0x03
diff --git a/spi25.c b/spi25.c
index 74db1005..d52dc3ae 100644
--- a/spi25.c
+++ b/spi25.c
@@ -351,7 +351,16 @@ static int spi_simple_write_cmd(struct flashctx *const flash, const uint8_t op,
static int spi_write_extended_address_register(struct flashctx *const flash, const uint8_t regdata)
{
- const uint8_t op = flash->chip->wrea_override ? : JEDEC_WRITE_EXT_ADDR_REG;
+ uint8_t op;
+ if (flash->chip->feature_bits & FEATURE_4BA_EAR_C5C8) {
+ op = JEDEC_WRITE_EXT_ADDR_REG;
+ } else if (flash->chip->feature_bits & FEATURE_4BA_EAR_1716) {
+ op = ALT_WRITE_EXT_ADDR_REG_17;
+ } else {
+ msg_cerr("Flash misses feature flag for extended-address register.\n");
+ return -1;
+ }
+
struct spi_command cmds[] = {
{
.readarr = 0,
@@ -394,7 +403,7 @@ static int spi_prepare_address(struct flashctx *const flash, uint8_t cmd_buf[],
cmd_buf[4] = (addr >> 0) & 0xff;
return 4;
} else {
- if (flash->chip->feature_bits & FEATURE_4BA_EAR_C5C8) {
+ if (flash->chip->feature_bits & FEATURE_4BA_EAR_ANY) {
if (spi_set_extended_address(flash, addr >> 24))
return -1;
} else if (addr >> 24) {