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authorSubrata Banik <subratabanik@google.com>2022-11-18 16:43:16 +0530
committerEdward O'Callaghan <quasisec@chromium.org>2022-11-25 22:02:27 +0000
commitcf030c000c9cfc5cbb3fbf3f1473d1591a6d891c (patch)
treebf66b58234bb79a50a292d7b41cff87b0e5fe121 /Makefile.d/pci_old_get_dev_test.c
parentcfb8df9d57ed1d08cff1b847d9669eb8663f587b (diff)
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ichspi: Fix number of bytes for HW seq operations
This patch fixes a potential issue where the SPI controller register HSFC.FDBC (bits 24-29) value gets incorrectly calculated while passing the `len` as `0` instead of `1`. As per Intel EDS, `0b` in the FDBC represents 1 byte while `0x3f` represents 64-bytes to be transferred. The number of bytes transferred is the value of this field plus 1. If we would like to transfer 1 byte then we need to set `0b` in FDBC for operations like read, write, flash id as to account for the `set byte count` hence, the `len` argument should be `1`. Additionally, as per EDS, the FDBC field is ignored for any block erase command. BUG=b:258280679 TEST=Able to build flashrom and perform below operations on Google, Rex and Google, Kano/Taeko. During `--wp-disable` HW seq operation that requires 1 byte data transfer. HSFC.FDBC value while passing `len` as `0` = 0x3f (represents 64-byte) HSFC.FDBC value while passing `len` as `1` = 0x0 (represents 1-byte) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5b911655649c693e576497520687d7810bbd3c54 Reviewed-on: https://review.coreboot.org/c/flashrom/+/69789 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Makefile.d/pci_old_get_dev_test.c')
0 files changed, 0 insertions, 0 deletions