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| author | Edward O'Callaghan <quasisec@google.com> | 2020-05-06 15:24:25 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-05-06 12:20:40 +0000 |
| commit | 76c582d9727c9fe5c61aef74548b812fb299f9b5 (patch) | |
| tree | 7f76895bb0909137d76542787f8b8175485f4c3c /atavia.c | |
| parent | ba6003fbff506229fc21658c3204083ee28235d2 (diff) | |
| download | flashrom-76c582d9727c9fe5c61aef74548b812fb299f9b5.tar.gz flashrom-76c582d9727c9fe5c61aef74548b812fb299f9b5.tar.bz2 flashrom-76c582d9727c9fe5c61aef74548b812fb299f9b5.zip | |
realtek_mst_i2c_spi.c: Fix _spi_send_command cb for erasures
Before issuing SPI opcodes into 0x61 the top three BITS of
0x60 need to be carefully crafted. Correctly craft these
in the case of SPI erasures and document this registers
expectations. Clean up remaining debug comments while we
are here.
BUG=b:152558985,b:148745673
BRANCH=none
TEST=flashrom -p realtek_mst_i2c_spi:bus=8 -E &&
flashrom -p realtek_mst_i2c_spi:bus=8 -r foo &&
hexdump -C foo
Change-Id: Ib11ba8f63b11a1c5ebaa68deb7971648de8c2ecd
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Diffstat (limited to 'atavia.c')
0 files changed, 0 insertions, 0 deletions