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| author | Edward O'Callaghan <quasisec@google.com> | 2022-02-26 11:37:08 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2022-05-04 03:05:20 +0000 |
| commit | 5f0d2aa6c83e904c5216da8d7281119fe5f1f4b9 (patch) | |
| tree | 3cafddbb96d642c4fa5ceab4115cc966e48bc362 /board_enable.c | |
| parent | 0f388acaba981c6c3ebee10528d88e42195f805f (diff) | |
| download | flashrom-5f0d2aa6c83e904c5216da8d7281119fe5f1f4b9.tar.gz flashrom-5f0d2aa6c83e904c5216da8d7281119fe5f1f4b9.tar.bz2 flashrom-5f0d2aa6c83e904c5216da8d7281119fe5f1f4b9.zip | |
board_enable.c: Port to use pcidev_find_vendorclass() helper
Change-Id: I3d8e3dbd5eeb057d7c959a82678cca2345fc69d9
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Diffstat (limited to 'board_enable.c')
| -rw-r--r-- | board_enable.c | 24 |
1 files changed, 9 insertions, 15 deletions
diff --git a/board_enable.c b/board_enable.c index d7408064..7b9e9f64 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1555,23 +1555,17 @@ static int intel_ich_gpio_set(int gpio, int raise) int i, allowed; /* First, look for a known LPC bridge */ - for (dev = pacc->devices; dev; dev = dev->next) { - uint16_t device_class; - /* libpci before version 2.2.4 does not store class info. */ - device_class = pci_read_word(dev, PCI_CLASS_DEVICE); - if ((dev->vendor_id == 0x8086) && - (device_class == 0x0601)) { /* ISA bridge */ - /* Is this device in our list? */ - for (i = 0; intel_ich_gpio_table[i].id; i++) - if (dev->device_id == intel_ich_gpio_table[i].id) - break; - - if (intel_ich_gpio_table[i].id) - break; - } + dev = pcidev_find_vendorclass(0x8086, 0x0601); /* ISA bridge */ + if (!dev) { + msg_perr("\nERROR: No known Intel LPC bridge found.\n"); + return -1; } + /* Is this device in our list? */ + for (i = 0; intel_ich_gpio_table[i].id; i++) + if (dev->device_id == intel_ich_gpio_table[i].id) + break; - if (!dev) { + if (!intel_ich_gpio_table[i].id) { msg_perr("\nERROR: No known Intel LPC bridge found.\n"); return -1; } |