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authorEvgeny Zinoviev <me@ch1p.com>2020-03-09 03:05:42 +0300
committerNico Huber <nico.h@gmx.de>2020-03-19 09:42:40 +0000
commite65aa96fd35f8734f44e8f854838fc59bdd599db (patch)
treecd176311a16c745be4936c5152b1557508e81a2a /chipset_enable.c
parentb1e558389a6124df202bc03b336518fc93209cb5 (diff)
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chipset_enable: Mark Intel HM75 as DEP
Tested reading and writing on a Samsung laptop (see CB:39388). Change-Id: Idbb9c719a6f794a35293bb3b167cc1491d24d4fa Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'chipset_enable.c')
-rw-r--r--chipset_enable.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/chipset_enable.c b/chipset_enable.c
index 4afb0e44..ae8269a2 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -1832,7 +1832,7 @@ const struct penable chipset_enables[] = {
{0x8086, 0x1e57, B_FS, DEP, "Intel", "HM77", enable_flash_pch7},
{0x8086, 0x1e58, B_FS, NT, "Intel", "UM77", enable_flash_pch7},
{0x8086, 0x1e59, B_FS, DEP, "Intel", "HM76", enable_flash_pch7},
- {0x8086, 0x1e5d, B_FS, NT, "Intel", "HM75", enable_flash_pch7},
+ {0x8086, 0x1e5d, B_FS, DEP, "Intel", "HM75", enable_flash_pch7},
{0x8086, 0x1e5e, B_FS, NT, "Intel", "HM70", enable_flash_pch7},
{0x8086, 0x1e5f, B_FS, DEP, "Intel", "NM70", enable_flash_pch7},
{0x8086, 0x1f38, B_FS, DEP, "Intel", "Avoton/Rangeley", enable_flash_silvermont},