diff options
| author | Nikolai Artemiev <nartemiev@google.com> | 2022-03-08 01:07:01 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2022-04-05 23:50:27 +0000 |
| commit | bd2d070f9fb2c8d89276a9e17ae7e4db1356d26e (patch) | |
| tree | 5e1cf2d63e3d1a2ed021e869ae521cadfe6208f0 /coreboot_tables.h | |
| parent | 9b20174fda038ef633af2163c9b1570f4dbf9a37 (diff) | |
| download | flashrom-bd2d070f9fb2c8d89276a9e17ae7e4db1356d26e.tar.gz flashrom-bd2d070f9fb2c8d89276a9e17ae7e4db1356d26e.tar.bz2 flashrom-bd2d070f9fb2c8d89276a9e17ae7e4db1356d26e.zip | |
writeprotect.c: refactor and fix wp_mode functions
This is a follow up on commit 12dbc4e04508aecfff53ad95b6f68865da1b4f07.
Use a lookup table in get_wp_mode() and drop the srp_bit_present check,
since a chip without SRP is just FLASHROM_WP_MODE_DISABLED.
Add a srp_bit_present check to set_wp_mode() if the mode requires it.
BUG=b:182223106
BRANCH=none
TEST=flashrom --wp-{enable,disable,status} on AMD dut
Change-Id: Ib6c347453f9216e5816e4ed35bf9783fd3c720e0
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Diffstat (limited to 'coreboot_tables.h')
0 files changed, 0 insertions, 0 deletions