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| author | Nico Huber <nico.h@gmx.de> | 2018-03-13 18:01:05 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-10-03 13:10:17 +0000 |
| commit | 57dbd64b33143964bb8eb91d33d72a2147f0091c (patch) | |
| tree | 1606d103406bf36144602971ca2ac970d3a61482 /flashchips.c | |
| parent | 3eb5a8c82c00769bffc95c2c6c479de6d20dbd09 (diff) | |
| download | flashrom-57dbd64b33143964bb8eb91d33d72a2147f0091c.tar.gz flashrom-57dbd64b33143964bb8eb91d33d72a2147f0091c.tar.bz2 flashrom-57dbd64b33143964bb8eb91d33d72a2147f0091c.zip | |
flashchips: Add Spansion 25FL256S......0
The Spansion 25SFL256S supports 4BA through an extended address register,
a 4BA mode set by bit 7 of that register, or native 4BA instructions.
Enable the former only for now.
Unfortunately the S25SF256S uses another instruction to write the exten-
ded address register. So we add an override for the instruction byte.
Change-Id: I0a95a81dfe86434f049215ebd8477392391b9efc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Tested-by: Michael Fuckner <michael@fuckner.net>
Reviewed-on: https://review.coreboot.org/25132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'flashchips.c')
| -rw-r--r-- | flashchips.c | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/flashchips.c b/flashchips.c index 054ca7a9..78538492 100644 --- a/flashchips.c +++ b/flashchips.c @@ -12516,6 +12516,48 @@ const struct flashchip flashchips[] = { }, { + .vendor = "Spansion", + .name = "S25FL256S......0", /* hybrid: 32 (top or bottom) 4 kB sub-sectors + 64 kB sectors */ + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL256, + .total_size = 32768, + .page_size = 256, + /* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_EXT_ADDR, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + /* This chip supports erasing of the 32 so-called "parameter sectors" with + * opcode 0x20. Trying to access an address outside these 4kB blocks does + * have no effect on the memory contents, but sets a flag in the SR. + .eraseblocks = { + {4 * 1024, 32}, + {64 * 1024, 254} // inaccessible + }, + .block_erase = spi_block_erase_20, + }, { */ + .eraseblocks = { { 64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { { 32768 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { { 32768 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp2_ep_srwd, /* TODO: SR2 and many others */ + .unlock = spi_disable_blockprotect_bp2_srwd, /* TODO: various other locks */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + .wrea_override = 0x17, + }, + + { .vendor = "SST", .name = "SST25LF020A", .bustype = BUS_SPI, |