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author | Michael Niewöhner <foss@mniewoehner.de> | 2021-09-21 18:03:29 +0200 |
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committer | Nico Huber <nico.h@gmx.de> | 2021-09-26 14:57:24 +0000 |
commit | 21bf91d93fa384c00ff4a48f956b21c0ec4aaa33 (patch) | |
tree | dd9fc298c2e501a140defe300042caab6c1a056c /ft2232_spi.c | |
parent | aedfb7ebd90ca5958ffeb878b08c45cc51f974d6 (diff) | |
download | flashrom-21bf91d93fa384c00ff4a48f956b21c0ec4aaa33.tar.gz flashrom-21bf91d93fa384c00ff4a48f956b21c0ec4aaa33.tar.bz2 flashrom-21bf91d93fa384c00ff4a48f956b21c0ec4aaa33.zip |
ft2232_spi: clarify the comment about gpio configuration
The comment explaining gpio levels might be easily misunderstood when
the reader misses the word `output`. Add an explicit description of
handling of the GPIOL* pins to avoid that and make things even more
clear.
Change-Id: Iaceec889a65ead8cdde917f61b2a9695d440f781
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/57808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'ft2232_spi.c')
-rw-r--r-- | ft2232_spi.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/ft2232_spi.c b/ft2232_spi.c index 0962f1c1..df156d6f 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -89,8 +89,11 @@ static const struct dev_entry devs_ft2232spi[] = { * "set data bits low byte" MPSSE command that sets the initial * state and the direction of the I/O pins. `cs_bits` pins default * to high and will be toggled during SPI transactions. All other - * output pins will be kept low all the time. On exit, all pins - * will be reconfigured as inputs. + * output pins will be kept low all the time. For some programmers, + * some reserved GPIOL* pins are used as outputs. Free GPIOL* pins + * are configured as inputs, while it's possible to use one of them + * as additional CS# signal through the parameter `csgpiol`. On exit, + * all pins will be reconfigured as inputs. * * The pin offsets are as follows: * TCK/SK is bit 0. |