diff options
| author | Mattias Mattsson <vitplister@gmail.com> | 2010-08-15 22:35:31 +0000 |
|---|---|---|
| committer | Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> | 2010-08-15 22:35:31 +0000 |
| commit | d7ed7f7e0b3cc9188672646a60c1c70f350ea52d (patch) | |
| tree | 0f3a1dc79353c40489c995928dadf04783158390 /gfxnvidia.c | |
| parent | ead705fc856515e1bfff4eddab3e971f45f7a599 (diff) | |
| download | flashrom-d7ed7f7e0b3cc9188672646a60c1c70f350ea52d.tar.gz flashrom-d7ed7f7e0b3cc9188672646a60c1c70f350ea52d.tar.bz2 flashrom-d7ed7f7e0b3cc9188672646a60c1c70f350ea52d.zip | |
Check availability of GPO lines on Intel PIIX4
This patch changes the intel_piix4_gpo_set() function to always check
the GENCFG and XBCS registers for the availability of the
requested GPO line before raising/lowering it and fails otherwise. It
makes no attempt to bypass the values in these configuration
registers.
The old flashrom code did consider it safe to reprogram (multiplexed)
GPO:s 22-26 without checking the value of the controlling register
(GENCFG). I do not really know why.
I have tested this patch on an Asus P2B-N (needs GPO18 low) and MSI
MS-6163 Pro (needs GPO14 high).
The information for these registers are from the Intel "82371AB
PCI-TO-ISA / IDE XCELERATOR (PIIX4)" datasheet available here:
http://www.intel.com/design/intarch/datashts/29056201.pdf
Corresponding to flashrom svn r1142.
Signed-off-by: Mattias Mattsson <vitplister@gmail.com>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Diffstat (limited to 'gfxnvidia.c')
0 files changed, 0 insertions, 0 deletions