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author | Nikolai Artemiev <nartemiev@google.com> | 2021-11-22 13:18:49 +1100 |
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committer | Edward O'Callaghan <quasisec@chromium.org> | 2022-04-05 02:23:54 +0000 |
commit | e5389d1b8fa18932a7aa3be5fee094c5023d1251 (patch) | |
tree | f4df14bd9c260c108d156d2e7e573c81cb2cd3f7 /it87spi.c | |
parent | 7dcd0deafe667fdbec529285077149e0832acd69 (diff) | |
download | flashrom-e5389d1b8fa18932a7aa3be5fee094c5023d1251.tar.gz flashrom-e5389d1b8fa18932a7aa3be5fee094c5023d1251.tar.bz2 flashrom-e5389d1b8fa18932a7aa3be5fee094c5023d1251.zip |
spi25_statusreg: inline spi_write_register_flag()
Creating the entire SPI command that should be sent to the chip in
spi_write_register() is simpler than splitting it across two functions
that have to pass multiple parameters between them.
Additionally, having separate spi_write_register_flag() function
provided little benefit, as it was only ever called from
spi_write_register().
BUG=b:195381327,b:153800563
BRANCH=none
TEST=flashrom -{r,w,E}
TEST=Tested with a W25Q128.W flash on a kasumi (AMD) dut.
Read SR1/SR2 with --wp-status and activated various WP ranges
that toggled bits in both SR1 and SR2.
Change-Id: I4996b0848d0ed09032bad2ab13ab1f40bbfc0304
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59528
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'it87spi.c')
0 files changed, 0 insertions, 0 deletions