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authorEdward O'Callaghan <quasisec@google.com>2020-03-26 00:00:41 +1100
committerEdward O'Callaghan <quasisec@chromium.org>2020-05-04 00:52:42 +0000
commitd97f87b00cc8301b91023301a24e690146d74cef (patch)
tree17b3fe03e064bcafbdc74d3473a80983ee9ec0ff /meson.build
parent3ef0df067b4f14c230a411b2e3726492e60ae24b (diff)
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Initial Realtek MST i2c_spi support
This spi master allows for programming of a Realtek RTD2142 MST with external SPI flash chip routed via its internal i2c transport mechanism. BUG=b:152558985,b:148745673 BRANCH=none TEST=echo "00000000:0004ffff fw" > layout && \ flashrom -p realtek_mst_i2c_spi:bus=8 -l layout -i fw:dump.bin -r && \ flashrom -p realtek_mst_i2c_spi:bus=8 -l layout -i fw:dump.bin -w && \ flashrom -p realtek_mst_i2c_spi:bus=8 --flash-size && \ flashrom -p realtek_mst_i2c_spi:bus=8 --flash-name Change-Id: I892e0be776fe605e69fb39c77abf3016591d7123 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40667 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Shiyu Sun <sshiyu@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'meson.build')
-rw-r--r--meson.build5
1 files changed, 5 insertions, 0 deletions
diff --git a/meson.build b/meson.build
index 699370a6..5d8e630e 100644
--- a/meson.build
+++ b/meson.build
@@ -64,6 +64,7 @@ config_serprog = get_option('config_serprog')
config_usbblaster_spi = get_option('config_usbblaster_spi')
config_stlinkv3_spi = get_option('config_stlinkv3_spi')
config_lspcon_i2c_spi = get_option('config_lspcon_i2c_spi')
+config_realtek_mst_i2c_spi = get_option('config_realtek_mst_i2c_spi')
cargs = []
deps = []
@@ -288,6 +289,10 @@ if config_lspcon_i2c_spi
srcs += 'lspcon_i2c_spi.c'
cargs += '-DCONFIG_LSPCON_I2C_SPI=1'
endif
+if config_realtek_mst_i2c_spi
+ srcs += 'realtek_mst_i2c_spi.c'
+ cargs += '-DCONFIG_REALTEK_MST_I2C_SPI=1'
+endif
# bitbanging SPI infrastructure
if config_bitbang_spi