sb600spi.c: Use SPI100 bit mappings

On AMD SoCs that use SPI100 engine, flashrom has been using legacy
spi100 register and bit mappings when programming the engine -
specifically when programming the opcode and triggering their execution.
---------------------------------------------------------------------
| Register Name | Legacy SPI100 mapping  | Updated SPI100 mapping   |
|---------------|------------------------|--------------------------|
| Opcode        |  Offset 0 from SPI BAR | Offset 0x45 from SPI BAR |
|               |  Bits 0:7              | Bits 0:7                 |
|---------------|------------------------|--------------------------|
| Execute Cmd   |  Offset 2 from SPI BAR | Offset 0x47 from SPI BAR |
|               |  Bit 1                 | Bit 7                    |
---------------------------------------------------------------------
These legacy register mappings are removed in upcoming generations of
AMD SoCs. Stop using the legacy spi100 registers. For more details about
SPI100 refer to document: 56569-A1 Rev 3.01

BUG=b:228238107
TEST=Build and deploy flashrom in Skyrim. Ensure that flashrom is able
to detect the SPI ROM chip, read from it and write to it successfully.
Ran flashrom_tester on Dewatt (Cezanne SoC), Dalboz (Picasso SoC)
successfully and ensured that all the tests passed.

Change-Id: If42130757331f4294b5a42c848557d3287f24fc3
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>

1 files changed, 16 insertions, 2 deletions

diff --git a/sb600spi.c b/sb600spi.c
index 6f8cc40a..b1e140ba 100644
--- a/sb600spi.c
+++ b/sb600spi.c
@@ -53,6 +53,10 @@ enum amd_chipset {
 #define FIFO_SIZE_OLD		8
 #define FIFO_SIZE_YANGTZE	71
 
+#define SPI100_CMD_CODE_REG	0x45
+#define SPI100_CMD_TRIGGER_REG	0x47
+#define   SPI100_EXECUTE_CMD	(1 << 7)
+
 struct sb600spi_data {
 	struct flashctx *flash;
 	uint8_t *spibar;
@@ -200,6 +204,16 @@ static void execute_command(uint8_t *sb600_spibar)
 	msg_pspew("done\n");
 }
 
+static void execute_spi100_command(uint8_t *sb600_spibar)
+{
+	msg_pspew("Executing... ");
+	mmio_writeb(mmio_readb(sb600_spibar + SPI100_CMD_TRIGGER_REG) | SPI100_EXECUTE_CMD,
+			sb600_spibar + SPI100_CMD_TRIGGER_REG);
+	while (mmio_readb(sb600_spibar + SPI100_CMD_TRIGGER_REG) & SPI100_CMD_TRIGGER_REG)
+		;
+	msg_pspew("done\n");
+}
+
 static int sb600_spi_send_command(const struct flashctx *flash, unsigned int writecnt,
 				  unsigned int readcnt,
 				  const unsigned char *writearr,
@@ -299,7 +313,7 @@ static int spi100_spi_send_command(const struct flashctx *flash, unsigned int wr
 	unsigned char cmd = *writearr++;
 	writecnt--;
 	msg_pspew("%s, cmd=0x%02x, writecnt=%d, readcnt=%d\n", __func__, cmd, writecnt, readcnt);
-	mmio_writeb(cmd, sb600_spibar + 0);
+	mmio_writeb(cmd, sb600_spibar + SPI100_CMD_CODE_REG);
 
 	int ret = check_readwritecnt(flash, writecnt, readcnt);
 	if (ret != 0)
@@ -317,7 +331,7 @@ static int spi100_spi_send_command(const struct flashctx *flash, unsigned int wr
 	}
 	msg_pspew("\n");
 
-	execute_command(sb600_spibar);
+	execute_spi100_command(sb600_spibar);
 
 	msg_pspew("Reading buffer: ");
 	for (count = 0; count < readcnt; count++) {