diff options
| author | Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> | 2012-12-29 15:04:12 +0000 |
|---|---|---|
| committer | Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> | 2012-12-29 15:04:12 +0000 |
| commit | 54aaa4ae2bb4026ae7acbf3e0aafe8542aaff2a4 (patch) | |
| tree | b394950b3bd52b2490e1da77a1c497516d6bfd06 /serprog.h | |
| parent | 9530a02212bd48aca32752250c4e2ec91e24d3b6 (diff) | |
| download | flashrom-54aaa4ae2bb4026ae7acbf3e0aafe8542aaff2a4.tar.gz flashrom-54aaa4ae2bb4026ae7acbf3e0aafe8542aaff2a4.tar.bz2 flashrom-54aaa4ae2bb4026ae7acbf3e0aafe8542aaff2a4.zip | |
Add support for Intel S33 series flash chips
This includes:
Bottom boot block:
* 16Mb/2MB:
QB25F160S33B8, QB25F016S33B8, QH25F160S33B8, QH25F016S33B8
* 32Mb/4MB:
QB25F320S33B8, QH25F320S33B8
* 64Mb/8MB:
QB25F640S33B8, QH25F640S33B8
Top boot block:
* 16Mb/2MB:
QB25F160S33T8, QB25F016S33T8, QH25F160S33T8, QH25F016S33T8
* 32Mb/4MB:
QB25F320S33T8, QH25F320S33T8
* 64Mb/8MB:
QB25F640S33T8, QH25F640S33T8
At least some seem to be marketed by other vendors (too?) but also with
Intel's vendor ID.
Besides a 0xC7 chip erase and a 0xD8 uniform 64kB block erase they
support also erasing the top/bottom 8 8kB blocks with opcode 0x40.
But since this command fails for all addresses outside those ranges,
it is not easily implemented with flashrom's current code base and
hence left out.
Corresponding to flashrom svn r1636.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Diffstat (limited to 'serprog.h')
0 files changed, 0 insertions, 0 deletions