chipset_enable: Add support for Intel Skylake / Kabylake

All publicly known Skylake / Kabylake / Sunrise Point PCH variants
share the same register interface [1..6]. Although all SPI configu-
ration is now done through the SPI PCI device 1f.5, we can't probe
for it directly since its PCI vendor and device IDs are usually hid-
den.

To work around the hidden IDs, we use another PCI accessor that doesn't
rely on the OS seeing the PCI device.

This handles SPI flashes only. While booting from LPC is still sup-
ported, it seems nobody uses it any more.

Some additional PCI IDs were gathered from driveridentifier.com.

TEST=Compiled with B150 set to NT (instead of BAD) and checked for
     sane register readings.

[1] 6th Generation Intel® Core(TM) Processor Families I/O Platform
    Datasheet - Volume 1 of 2
    Revision 002EN
    Document Number 332995

[2] 6th Generation Intel® Processor I/O Datasheet for U/Y Platforms
    Volume 2 of 2
    Revision 001EN
    Document Number 332996

[3] 7th Generation Intel® Processor Families I/O Platform
    Datasheet - Volume 1 of 2
    Revision 002
    Document Number 334658

[4] 7th Generation Intel® Processor Families I/O for U/Y Platforms
    Datasheet - Volume 2 of 2
    Revision 002
    Document Number 334659

[5] Intel® 100 Series and Intel® C230 Series Chipset Family Platform
    Controller Hub (PCH)
    Datasheet - Volume 1 of 2
    Revision 004EN
    Document Number 332690

[6] Intel® 100 Series Chipset Family Platform Controller Hub (PCH)
    Datasheet - Volume 2 of 2
    Revision 001EN
    Document Number 332691

Change-Id: I000819aff25fbe9764f33df85f040093b82cd948
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18925
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>

0 files changed, 0 insertions, 0 deletions