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| author | Nikolai Artemiev <nartemiev@google.com> | 2020-10-06 16:59:51 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-12-03 12:31:33 +0000 |
| commit | adbae0e2681a994520ea551bd2f66b06de0b0899 (patch) | |
| tree | a9ac2edd308fac78303ab0c2347b8a919720d6c0 /spi.h | |
| parent | f745d0e6ab85f84b482aeac2ac4975e26db57389 (diff) | |
| download | flashrom-adbae0e2681a994520ea551bd2f66b06de0b0899.tar.gz flashrom-adbae0e2681a994520ea551bd2f66b06de0b0899.tar.bz2 flashrom-adbae0e2681a994520ea551bd2f66b06de0b0899.zip | |
s25f.c: implement probing and block erasers for Spansion
This adds support for Spansion 25Fxxxxx chips. These chips
require their own probing logic because the first 6 bytes
returned by RDID must be examined to identify the chip.
New erase functions are required as the chips support multiple
sector layouts, and the default layout must be changed to be
able to erase the entire flash.
Adapted from cros flashrom at
`9c4c9a56b6a0370b383df9c75d71b3bd469e672d`.
BUG=b:153800073
TEST=builds
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Change-Id: I2d23f9c36ce8b2959807fbeee7f60e02444e3763
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Diffstat (limited to 'spi.h')
| -rw-r--r-- | spi.h | 6 |
1 files changed, 6 insertions, 0 deletions
@@ -111,6 +111,11 @@ #define JEDEC_BE_D7_OUTSIZE 0x04 #define JEDEC_BE_D7_INSIZE 0x00 +/* Block Erase 0xdc is supported by Spansion chips, takes 4 byte address */ +#define JEDEC_BE_DC 0xdc +#define JEDEC_BE_DC_OUTSIZE 0x05 +#define JEDEC_BE_DC_INSIZE 0x00 + /* Sector Erase 0x20 is supported by Macronix/SST chips. */ #define JEDEC_SE 0x20 #define JEDEC_SE_OUTSIZE 0x04 @@ -129,6 +134,7 @@ /* Status Register Bits */ #define SPI_SR_WIP (0x01 << 0) #define SPI_SR_WEL (0x01 << 1) +#define SPI_SR_ERA_ERR (0x01 << 5) #define SPI_SR_AAI (0x01 << 6) /* Write Status Enable */ |