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author | Nico Huber <nico.huber@secunet.com> | 2017-03-24 17:25:37 +0100 |
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committer | Nico Huber <nico.h@gmx.de> | 2017-07-28 12:30:21 +0000 |
commit | fa62294536a3ce5070e8d9065aaa1aa45031f910 (patch) | |
tree | 66152f87787e5c3c6ce2c9db903f8e1a70bd9311 /spi25_statusreg.c | |
parent | 1dc3d420831b0ee482aede5f46ba53a0d2de4b74 (diff) | |
download | flashrom-fa62294536a3ce5070e8d9065aaa1aa45031f910.tar.gz flashrom-fa62294536a3ce5070e8d9065aaa1aa45031f910.tar.bz2 flashrom-fa62294536a3ce5070e8d9065aaa1aa45031f910.zip |
ich_descriptors: Update for Intel Skylake
Interpretation of component clocks changed. Also more regions and more
masters are supported now. The number of regions (NR) is now static per
chipset (10 in the 100 Series case) and not coded into the descriptor
any more.
v2: o Use guess_ich_chipset() for read_ich_descriptors_from_dump().
o Update region extraction in `ich_descriptors_tool`.
TEST=Run `ich_descriptors_tool` over a 100 Series dump and checked
that output looks sane. Run `ich_descriptors_tool` over dumps
of five different older systems (1 x Sandy Bridge, 3 x Ivy Bridge,
1 x Haswell). Beside whitespace changes, regions not accounted
by `NR` are not printed any more.
Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18973
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'spi25_statusreg.c')
0 files changed, 0 insertions, 0 deletions