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| author | Nico Huber <nico.huber@secunet.com> | 2017-03-17 17:59:54 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-06-20 11:47:49 +0200 |
| commit | 512059118e9ff56d2b4f3c324db5e764e288ac68 (patch) | |
| tree | 7c3c384d1579b467135fd85dd9cfbb88abb4771c /sst_fwhub.c | |
| parent | d7c7552b4b7a94509a86404ee4bc9b0f2fdd7359 (diff) | |
| download | flashrom-512059118e9ff56d2b4f3c324db5e764e288ac68.tar.gz flashrom-512059118e9ff56d2b4f3c324db5e764e288ac68.tar.bz2 flashrom-512059118e9ff56d2b4f3c324db5e764e288ac68.zip | |
Handle Intel Wildcat Point *LP* like Lynx Point LP
The subtle difference was ignored when adding these chipsets. The
integrated Wildcat Point LP PCH is documented in [1].
I'm not sure how to account for "Broadwell H" which seems not publicly
documented. Maybe it's an unreleased HM9*, in which case the non-LP
path should be correct.
[1] Mobile 5th Generation Intel® Core(TM) Processor Family I/O,
Intel® Core(TM) M Processor Family I/O, Mobile Intel® Pentium® Processor
Family I/O, and Mobile Intel® Celeron® Processor Family I/O Datasheet
Revision 004
Document Number: 330837
Change-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18883
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'sst_fwhub.c')
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