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| author | Edward O'Callaghan <quasisec@google.com> | 2020-05-22 19:09:49 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-06-17 11:08:30 +0000 |
| commit | 76d2445d39592834ffd7ee70a0e2ce8e12ee45a3 (patch) | |
| tree | 421633f8d69a0f3eb422bb6795139ad28f6c8007 /tests/spi25.c | |
| parent | 3cc70c25f959afec4179971437c53b809cb3a9a3 (diff) | |
| download | flashrom-76d2445d39592834ffd7ee70a0e2ce8e12ee45a3.tar.gz flashrom-76d2445d39592834ffd7ee70a0e2ce8e12ee45a3.tar.bz2 flashrom-76d2445d39592834ffd7ee70a0e2ce8e12ee45a3.zip | |
tests/spi25.c: Add unit-test coverage of spi95.c
Add spi95.c unit-tests to spi25.c to avoid some clutter.
BUG=b:157280555
BRANCH=none
TEST=builds
Change-Id: I6de59451b82131b58114b268ff6dd0b18cd5952b
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'tests/spi25.c')
| -rw-r--r-- | tests/spi25.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/tests/spi25.c b/tests/spi25.c index 99325742..aa1eea01 100644 --- a/tests/spi25.c +++ b/tests/spi25.c @@ -168,3 +168,22 @@ void probe_spi_at25f_test_success(void **state) will_return(__wrap_spi_send_command, AT25F_RDID_INSIZE); assert_int_equal(0, probe_spi_at25f(&flashctx)); } + +/* spi95.c */ +void probe_spi_st95_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + /* chip total size < 64K. */ + uint32_t rdid_outsize = ST_M95_RDID_2BA_OUTSIZE; // 16 bit address + + will_return(__wrap_spi_send_command, rdid_outsize); + will_return(__wrap_spi_send_command, ST_M95_RDID); + will_return(__wrap_spi_send_command, ST_M95_RDID_INSIZE); + assert_int_equal(0, probe_spi_st95(&flashctx)); +} |