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| author | Nikolai Artemiev <nartemiev@google.com> | 2022-11-02 11:30:57 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2022-12-06 03:12:55 +0000 |
| commit | 49bcb78006d88189bb13513982f3fa734b441641 (patch) | |
| tree | 11586cf450e59b78d94a530b74028b04888da288 /writeprotect.c | |
| parent | 62ec7b7156e1b35da66f54f6d493b38a9e78f94c (diff) | |
| download | flashrom-49bcb78006d88189bb13513982f3fa734b441641.tar.gz flashrom-49bcb78006d88189bb13513982f3fa734b441641.tar.bz2 flashrom-49bcb78006d88189bb13513982f3fa734b441641.zip | |
writeprotect,ichspi,spi25: handle register access constraints
Make the spi25 register read/write functions return SPI_INVALID_OPCODE
if the programmer blocks the read/write opcode for the register.
Likewise, make ichspi read/write register functions return
SPI_INVALID_OPCODE for registers >SR1 as they cannot be accessd.
Make writeprotect ignore SPI_INVALID_OPCODE unless it is trying to
read/write SR1, which should always be supported.
BUG=b:253715389,b:253713774,b:240229722
BRANCH=none
TEST=flashrom --wp-{enable,disable,range,list,status} on dedede
Change-Id: I2145749dcc51f4556550650dab5aa1049f879c45
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/69129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Diffstat (limited to 'writeprotect.c')
| -rw-r--r-- | writeprotect.c | 29 |
1 files changed, 25 insertions, 4 deletions
diff --git a/writeprotect.c b/writeprotect.c index 49586b4b..d8ffa689 100644 --- a/writeprotect.c +++ b/writeprotect.c @@ -19,6 +19,7 @@ #include <stdlib.h> #include <string.h> +#include "spi.h" #include "flash.h" #include "libflashrom.h" #include "chipdrivers.h" @@ -30,18 +31,38 @@ */ static int wp_write_register(const struct flashctx *flash, enum flash_reg reg, uint8_t value) { + int ret; if ((flash->mst->buses_supported & BUS_PROG) && flash->mst->opaque.write_register) { - return flash->mst->opaque.write_register(flash, reg, value); + ret = flash->mst->opaque.write_register(flash, reg, value); + } else { + ret = spi_write_register(flash, reg, value); + } + + /* Writing SR1 should always be supported, ignore errors for other registers. */ + if (ret == SPI_INVALID_OPCODE && reg != STATUS1) { + msg_pdbg("%s: write to register %d not supported by programmer, ignoring.\n", __func__, reg); + ret = 0; } - return spi_write_register(flash, reg, value); + return ret; } static int wp_read_register(const struct flashctx *flash, enum flash_reg reg, uint8_t *value) { + int ret; if ((flash->mst->buses_supported & BUS_PROG) && flash->mst->opaque.read_register) { - return flash->mst->opaque.read_register(flash, reg, value); + ret = flash->mst->opaque.read_register(flash, reg, value); + } else { + ret = spi_read_register(flash, reg, value); } - return spi_read_register(flash, reg, value); + + /* Reading SR1 should always be supported, ignore errors for other registers. */ + if (ret == SPI_INVALID_OPCODE && reg != STATUS1) { + msg_pdbg("%s: read from register %d not is supported by programmer, " + "writeprotect operations will assume it contains 0x00.\n", __func__, reg); + *value = 0; + ret = 0; + } + return ret; } /** Read and extract a single bit from the chip's registers */ |