diff options
| -rw-r--r-- | include/programmer.h | 2 | ||||
| -rw-r--r-- | internal.c | 2 | ||||
| -rw-r--r-- | it87spi.c | 6 |
3 files changed, 5 insertions, 5 deletions
diff --git a/include/programmer.h b/include/programmer.h index 95e25ca6..1372e2be 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -372,7 +372,7 @@ int amd_imc_shutdown(struct pci_dev *dev); void enter_conf_mode_ite(uint16_t port); void exit_conf_mode_ite(uint16_t port); void probe_superio_ite(void); -int init_superio_ite(void); +int init_superio_ite(const struct programmer_cfg *cfg); #if CONFIG_LINUX_MTD == 1 /* trivial wrapper to avoid cluttering internal_init() with #if */ @@ -293,7 +293,7 @@ static int internal_init(const struct programmer_cfg *cfg) #if defined(__i386__) || defined(__x86_64__) /* Probe unconditionally for ITE Super I/O chips. This enables LPC->SPI translation on IT87* and * parallel writes on IT8705F. Also, this handles the manual chip select for Gigabyte's DualBIOS. */ - init_superio_ite(); + init_superio_ite(cfg); if (board_flash_enable(board_vendor, board_model, cb_vendor, cb_model)) { msg_perr("Aborting to be safe.\n"); @@ -321,7 +321,7 @@ static const struct spi_master spi_master_it87xx = { .probe_opcode = default_spi_probe_opcode, }; -static uint16_t it87spi_probe(uint16_t port) +static uint16_t it87spi_probe(const struct programmer_cfg *cfg, uint16_t port) { uint8_t tmp = 0; uint16_t flashport = 0; @@ -440,7 +440,7 @@ static uint16_t it87spi_probe(uint16_t port) return register_spi_master(&spi_master_it87xx, data); } -int init_superio_ite(void) +int init_superio_ite(const struct programmer_cfg *cfg) { int i; int ret = 0; @@ -458,7 +458,7 @@ int init_superio_ite(void) case 0x8718: case 0x8720: case 0x8728: - ret |= it87spi_probe(superios[i].port); + ret |= it87spi_probe(cfg, superios[i].port); break; default: msg_pdbg2("Super I/O ID 0x%04hx is not on the list of flash-capable controllers.\n", |