diff options
Diffstat (limited to 'flashchips.c')
-rw-r--r-- | flashchips.c | 234 |
1 files changed, 234 insertions, 0 deletions
diff --git a/flashchips.c b/flashchips.c index 5e036aca..9dd045eb 100644 --- a/flashchips.c +++ b/flashchips.c @@ -4422,6 +4422,240 @@ const struct flashchip flashchips[] = { { .vendor = "Intel", + .name = "25F160S33B8", + .bustype = BUS_SPI, + .manufacture_id = INTEL_ID, + .model_id = INTEL_25F160S33B8, + .total_size = 2048, + .page_size = 256, + /* OTP: 506B total (2x 8B, 30x 16B, 1x 10B); read 0x4B; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + /* This chip supports erasing of the 8 so-called "parameter blocks" with + * opcode 0x40. Trying to access an address outside these 8 8kB blocks does + * have no effect on the memory contents, but sets a flag in the SR. + .eraseblocks = { + {8 * 1024, 8}, + {64 * 1024, 31} // inaccessible + }, + .block_erase = spi_block_erase_40, + }, { */ + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_s33, + .unlock = spi_disable_blockprotect_s33, + .write = spi_chip_write_256, + .read = spi_chip_read, /* also fast read 0x0B */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Intel", + .name = "25F160S33T8", + .bustype = BUS_SPI, + .manufacture_id = INTEL_ID, + .model_id = INTEL_25F160S33T8, + .total_size = 2048, + .page_size = 256, + /* OTP: 506B total (2x 8B, 30x 16B, 1x 10B); read 0x4B; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + /* This chip supports erasing of the 8 so-called "parameter blocks" with + * opcode 0x40. Trying to access an address outside these 8 8kB blocks does + * have no effect on the memory contents, but sets a flag in the SR. + .eraseblocks = { + {64 * 1024, 31}, // inaccessible + {8 * 1024, 8} + }, + .block_erase = spi_block_erase_40, + }, { */ + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_s33, + .unlock = spi_disable_blockprotect_s33, + .write = spi_chip_write_256, + .read = spi_chip_read, /* also fast read 0x0B */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Intel", + .name = "25F320S33B8", + .bustype = BUS_SPI, + .manufacture_id = INTEL_ID, + .model_id = INTEL_25F320S33B8, + .total_size = 4096, + .page_size = 256, + /* OTP: 506B total (2x 8B, 30x 16B, 1x 10B); read 0x4B; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + /* This chip supports erasing of the 8 so-called "parameter blocks" with + * opcode 0x40. Trying to access an address outside these 8 8kB blocks does + * have no effect on the memory contents, but sets a flag in the SR. + .eraseblocks = { + {8 * 1024, 8}, + {64 * 1024, 63} // inaccessible + }, + .block_erase = spi_block_erase_40, + }, { */ + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_s33, + .unlock = spi_disable_blockprotect_s33, + .write = spi_chip_write_256, + .read = spi_chip_read, /* also fast read 0x0B */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Intel", + .name = "25F320S33T8", + .bustype = BUS_SPI, + .manufacture_id = INTEL_ID, + .model_id = INTEL_25F320S33T8, + .total_size = 4096, + .page_size = 256, + /* OTP: 506B total (2x 8B, 30x 16B, 1x 10B); read 0x4B; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + /* This chip supports erasing of the 8 so-called "parameter blocks" with + * opcode 0x40. Trying to access an address outside these 8 8kB blocks does + * have no effect on the memory contents, but sets a flag in the SR. + .eraseblocks = { + {64 * 1024, 63}, // inaccessible + {8 * 1024, 8} + }, + .block_erase = spi_block_erase_40, + }, { */ + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_s33, + .unlock = spi_disable_blockprotect_s33, + .write = spi_chip_write_256, + .read = spi_chip_read, /* also fast read 0x0B */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Intel", + .name = "25F640S33B8", + .bustype = BUS_SPI, + .manufacture_id = INTEL_ID, + .model_id = INTEL_25F640S33B8, + .total_size = 8192, + .page_size = 256, + /* OTP: 506B total (2x 8B, 30x 16B, 1x 10B); read 0x4B; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + /* This chip supports erasing of the 8 so-called "parameter blocks" with + * opcode 0x40. Trying to access an address outside these 8 8kB blocks does + * have no effect on the memory contents, but sets a flag in the SR. + .eraseblocks = { + {8 * 1024, 8}, + {64 * 1024, 127} // inaccessible + }, + .block_erase = spi_block_erase_40, + }, { */ + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_s33, + .unlock = spi_disable_blockprotect_s33, + .write = spi_chip_write_256, + .read = spi_chip_read, /* also fast read 0x0B */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Intel", + .name = "25F640S33T8", + .bustype = BUS_SPI, + .manufacture_id = INTEL_ID, + .model_id = INTEL_25F640S33T8, + .total_size = 8192, + .page_size = 256, + /* OTP: 506B total (2x 8B, 30x 16B, 1x 10B); read 0x4B; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + /* This chip supports erasing of the 8 so-called "parameter blocks" with + * opcode 0x40. Trying to access an address outside these 8 8kB blocks does + * have no effect on the memory contents, but sets a flag in the SR. + .eraseblocks = { + {64 * 1024, 127}, // inaccessible + {8 * 1024, 8} + }, + .block_erase = spi_block_erase_40, + }, { */ + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_s33, + .unlock = spi_disable_blockprotect_s33, + .write = spi_chip_write_256, + .read = spi_chip_read, /* also fast read 0x0B */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Intel", .name = "28F001BN/BX-B", .bustype = BUS_PARALLEL, .manufacture_id = INTEL_ID, |