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* Fix multiple detection of the same chipCarl-Daniel Hailfinger2011-05-071-0/+1
| | | | | | | | | | r1293 introduced a bug which caused probing to loop at the first found chip. Corresponding to flashrom svn r1296. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Idwer Vollering <vidwer@gmail.com>
* Add support for the Via VX855 chipsetJohn Schmerge2011-05-051-0/+1
| | | | | | | Corresponding to flashrom svn r1295. Signed-off-by: John Schmerge <jbschmerge@gmail.com> for Devon IT Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Revamp board-specific quirk handling, allow for laptop supportCarl-Daniel Hailfinger2011-05-053-125/+189
| | | | | | | | | | | | | | | | | | | | | | | | Handle board-specific quirks in three phases: 1. Before Super I/O probing (e.g. blacklisting of some Super I/O probes, or unhiding the Super I/O) 2. Before the laptop enforcement decision (e.g. whitelisting a laptop for flashing) 3. After chipset enabling (all current board enables) Implementation note: All entries in board_pciid_enables get an additional phase parameter. Alternative variants (3 tables instead of 1) also have their downsides, and I chose table bloat over table multiplication). With this patch, it should be possible to whitelist supported laptops with a matching entry (phase P2) in board_pciid_enables which points to a function setting laptop_ok=1. (In case DMI is broken, matching might be a little bit more difficult, but it is still doable.) Corresponding to flashrom svn r1294. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
* Constify flashchips arrayCarl-Daniel Hailfinger2011-05-047-40/+53
| | | | | | | | | This moves 99.5% of the .data section to .rodata (which ends up in .text). Corresponding to flashrom svn r1293. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Revert MMIO space writes on shutdown as neededCarl-Daniel Hailfinger2011-05-035-20/+157
| | | | | | | | | | | | | | | | | | Reversible MMIO space writes now use rmmio_write*(). Reversible PCI MMIO space writes now use pci_rmmio_write*(). If a MMIO value needs to be queued for restore without writing it, use rmmio_val*(). MMIO space writes which are one-shot (e.g. communication with some chip) should continue to use the permanent mmio_write* variants. Corresponding to flashrom svn r1292. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> David tested it successfully on some NM10/ICH7 platforms which switch between SPI and LPC targets (x86 BIOS ROM vs. EC firmware ROM). Acked-by: David Hendricks <dhendrix@google.com>
* Improve output in case run_opcode failsStefan Tauner2011-04-291-5/+20
| | | | | | | Corresponding to flashrom svn r1291. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
* ichspi: Increase timeout to 60s for atomic operationsMichael Karcher2011-04-291-4/+18
| | | | | | | Corresponding to flashrom svn r1290. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add support for more than one Super I/O or EC per machineCarl-Daniel Hailfinger2011-04-276-159/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | Flashrom currently only supports exactly one Super I/O or Embedded Controller, and this means quite a few notebooks and a small subset of desktop/server boards cannot be handled reliably and easily. Allow detection and initialization of up to 3 Super I/O and/or EC chips. WARNING! If a Super I/O or EC responds on multiple ports (0x2e and 0x4e), the code will do the wrong thing (namely, initialize the hardware twice). I have no idea if we should handle such situations, and whether we should ignore the second chip with identical ID or not. Initializing the hardware twice for the IT87* family is _not_ a problem, but I don't know how well IT85* can handle it (and whether IT85* would listen at more than one port anyway). Corresponding to flashrom svn r1289. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Thanks to Thomas Schneider for testing on a board with ITE IT87* SPI. Test report (success) is here: http://paste.flashrom.org/view.php?id=379 Thanks to David Hendricks for testing on a Google Cr-48 laptop with ITE IT85* EC SPI. Test report (success) is here: http://www.flashrom.org/pipermail/flashrom/2011-April/006275.html Acked-by: David Hendricks <dhendrix@google.com>
* Remove delays in JEDEC erase sequenceMichael Karcher2011-04-151-18/+27
| | | | | | | | | | | | | | | | | | | It is extremely unlikely that a chip not requiring delays in probe does require them in erase. We observed unreliable erasing with a SST49LF004A with these delays, so remove them if the are not required. In review, I got the hint that "probe_jedec goes further by making that call conditional on nonzero delay". I decided to ignore that. For internal_delay, the small amount of clock cycles wasted for calling programmer_delay(0) is negligible compared to LPC cycle times. It might be an issue for 5 wasted bytes on the serial line in serprog. OTOH, flash erase is still slow compared to 6*5 bytes on a serial port at reasonable speed. Corresponding to flashrom svn r1288. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Remove erase_chip_stm50flw0x0xMichael Karcher2011-04-143-55/+0
| | | | | | | | | | | | | | | | As the comment indicates, that function is not a chip erase function at all, but a function calling a block eraser in a loop. So it adds no extra value to what we already have in the block_eraser infrastructure. Furthermore, that function assumes a uniform sector size layout, but is referenced from flash chip with non-uniform sector size layout, which is just wrong. Corresponding to flashrom svn r1287. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Board enable for Foxconn 6150K8MD-8EKRSHMichael Karcher2011-04-142-0/+3
| | | | | | | | | | | | | | | Reported by: wickberg@student.chalmers.se flashrom -V: http://paste.flashrom.org/view.php?id=452 lspci: http://paste.flashrom.org/view.php?id=453 (note that the flashrom dump is with a foreign chip. That board is originally equipped with an PMC Pm49FL004. Corresponding to flashrom svn r1286. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* List AMD SB850 as supported (it has the same PCI ID as SB700)Stefan Tauner2011-04-021-1/+1
| | | | | | | | | | Success report at http://flashrom.org/pipermail/flashrom/2011-March/006072.html Corresponding to flashrom svn r1285. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Idwer Vollering <vidwer@gmail.com>
* Coreboot table handling: make debug message msg_pdbgStefan Reinauer2011-04-011-1/+1
| | | | | | | Corresponding to flashrom svn r1284. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Fix typo in chipset_enable.cStefan Reinauer2011-03-291-1/+1
| | | | | | | Corresponding to flashrom svn r1283. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Idwer Vollering <vidwer@gmail.com>
* Update port of flashrom package to Mac OS X using DirectHWStefan Reinauer2011-03-183-4/+4
| | | | | | | | | | http://www.coreboot.org/DirectHW Corresponding to flashrom svn r1282. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
* Proper error handling for ICH/VIA SPICarl-Daniel Hailfinger2011-03-171-22/+80
| | | | | | | | | | | | | | Use 16-bit values for bit masks in 16-bit registers. Check for SPI Cycle In Progress and wait up to 60 ms. Do not touch reserved bits. Reduce SPI cycle timeout from 60 s to 60 ms. Clear transaction errors caused by our own SPI accesses. Add better debugging in case the hardware misbehaves. Corresponding to flashrom svn r1281. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Fix and improve libpayload platform supportPatrick Georgi2011-03-084-2/+45
| | | | | | | | | | | | | | - Fix various minor compile issues (eg. include necessary standard headers) - Fix compilation of libpayload code paths - Provide libpayload support in Makefile - Add make target "libflashrom.a" which links non-CLI code to static library Corresponding to flashrom svn r1280. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Tested-with-DOS-crosscompiler-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Various IT85* cleanups and fixesCarl-Daniel Hailfinger2011-03-083-19/+32
| | | | | | | | | | | | | | | | | | | | Fix a few typos. Change the EC memory region mapping name. Drop unused function parameter. Use mmio_writeb()/mmio_readb() to get reliable access to volatile memory locations instead of plain pointer access which is optimized away by gcc. Use own it85_* SPI high-level chip read/write functions instead of relying on unrelated ICH functions. Corresponding to flashrom svn r1279. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> David writes: I applied the patch against the Chromium OS branch and successfully tested read and write operations on a Cr48. Acked-by: David Hendricks <dhendrix@google.com>
* Fix compilation if CONFIG_INTERNAL=noCarl-Daniel Hailfinger2011-03-083-4/+8
| | | | | | | | | | | Fix compilation if everything except CONFIG_SATAMV is no. Do not compile in PCI support for wiki printing if no PCI devices are supported. Corresponding to flashrom svn r1278. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
* Fix broken compilation caused by a typo in r1275Idwer Vollering2011-03-071-1/+1
| | | | | | | Corresponding to flashrom svn r1277. Signed-off-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Idwer Vollering <vidwer@gmail.com>
* Mark Macronix MX25L1605D as fully testedSven Schnelle2011-03-071-1/+1
| | | | | | | Corresponding to flashrom svn r1276. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* SST39SF512 is testedMichael Karcher2011-03-071-1/+1
| | | | | | | | | Flashrom -V -w: http://paste.flashrom.org/view.php?id=395 Corresponding to flashrom svn r1275. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Remove vendorid parameter from pcidev_init()Carl-Daniel Hailfinger2011-03-0715-63/+18
| | | | | | | | | | | | | | | Simplify pcidev_init by killing the vendorid parameter which was pretty useless anyway since it was present in the pcidevs parameter as well. This also allows us to handle multiple programmers with different vendor IDs in the same driver. Fix compilation of flashrom with only the nicrealtek driver. Corresponding to flashrom svn r1274. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
* Add a board enable for Asus P4P800-VMDiego Elio Pettenò2011-03-061-0/+2
| | | | | | | | | | | | | Only list the memory controller PCI IDs because the only other subsystem mentioned is used by network and sound interfaces both of which can be turned off in BIOS. Tested on a board rev 1.85. Corresponding to flashrom svn r1273. Signed-off-by: Diego Elio Pettenò <flameeyes@gmail.com> Acked-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Stefan Reinauer <stepan@coreboot.org>
* Mark PMC Pm49FL004, SST SST49LF002A/B, SST SST49LF004A/B and ↵Idwer Vollering2011-03-061-4/+4
| | | | | | | | | Winbond_W39V040FB as write tested Corresponding to flashrom svn r1272. Signed-off-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add Gigabyte GA-MA780G-UD3H to mainboard support listBernhard Geier2011-03-061-0/+1
| | | | | | | | | http://www.flashrom.org/pipermail/flashrom/2010-October/005117.html Corresponding to flashrom svn r1271. Signed-off-by: Bernhard Geier <geierb@geierb.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add support for ST M25PX16 and mark it as supportedCarl Worth2011-03-062-0/+30
| | | | | | | | | | Tests were performed with write and verify operations to 4 different M25PX16 chips with a Dediprog SF100. Corresponding to flashrom svn r1270. Signed-off-by: Carl Worth <carl.d.worth@intel.com> Acked-by: Idwer Vollering <vidwer@gmail.com>
* Mark SST49LF080A as fully testedBrandon Dowdy2011-03-062-1/+2
| | | | | | | | | | | | Mark EVGA nForce 780i board as supported. Full logs are here: http://www.flashrom.org/pipermail/flashrom/2011-January/005779.html Corresponding to flashrom svn r1269. Signed-off-by: Brandon Dowdy <brandonrd7@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add W39L040Michael Karcher2011-03-063-0/+47
| | | | | | | Corresponding to flashrom svn r1268. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add coreboot IDs to make manual selection of HP xw9400 possibleMichael Karcher2011-03-061-1/+1
| | | | | | | Corresponding to flashrom svn r1267. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Board-enable for GA-K8N51GMFMichael Karcher2011-03-062-1/+5
| | | | | | | | | | | | | | | | | | Gigabyte is not really helpful with their PCI IDs for us, the subsystem IDs used just mean "gigabyte northbridge" and "gigabyte southbridge". We should investigate whether autodetection of this board is causing interference with other boards. real version 2: Extend list of PCI IDs for nvidia southbridges. flashrom -V: http://paste.flashrom.org/view.php?id=326 lspic: http://paste.flashrom.org/view.php?id=328 superiotool: http://paste.flashrom.org/view.php?id=329 Corresponding to flashrom svn r1266. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add HP e-Vectra P2706TMichael Karcher2011-03-062-6/+24
| | | | | | | | | | | | | | Reported by: Michal Janke <jankeso@gmail.com> flashrom -V: http://paste.flashrom.org/view.php?id=370 lspci: http://paste.flashrom.org/view.php?id=371 superiotool: http://paste.flashrom.org/view.php?id=372 and http://www.flashrom.org/pipermail/flashrom/2011-March/005878.html Corresponding to flashrom svn r1265. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* I tested a few mainboards and flash chipsYul Rottmann2011-03-052-2/+4
| | | | | | | | | | | | Successfully tested MSI MS-7596 (785GM-E51). Successfully tested ASRock 890GX Extreme3. Successfully tested Winbond W25x80. Mention which GIGABYTE GA-MA78G-DS3H board revision was tested. Corresponding to flashrom svn r1264. Signed-off-by: Yul Rottmann <yulrottmann@bitel.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Update the ITE IT8500 EC support to match the current state of the ↵David Hendricks2011-02-284-13/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | flashrom-chromium tree This code has been deployed and tested to work on the Cr-48. There are a few caveats, though: - The boot BIOS straps register must be modified to select LPC. This can be done with the "select_bbs.sh" script (Install iotools at http://code.google.com/p/iotools/ before using select_bbs). - It is very important to disable power management daemons before running flashrom on this EC. I commented out the brute force method we use in the Chromium OS branch that disables powerd, since IIRC Carl-Daniel has a better approach in the works. - Due to dependencies which may be introduced by the OEM/ODM EC firmware, the code is not guaranteed to work for anything other than the Cr-48. Corresponding to flashrom svn r1263. Signed-off-by: David Hendricks <dhendrix@google.com> Carl-Daniel comments: Code is not hooked up yet because probing needs to be sorted out. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add generalized support for ITE IT8500/IT8502 embedded controllersDonald Huang2011-02-221-0/+262
| | | | | | | | | | | | | | The patch was developed by Google. It was tested for IT8500E on a Chrome OS platform and may require modification depending on ODM/OEM customization and EC firmware version. This patch is not officially supported by ITE Tech Inc. Corresponding to flashrom svn r1262. Signed-off-by: Donald Huang <donald.huang@ite.com.tw> Signed-off-by: Yung-chieh Lo <yjlou@google.com> Signed-off-by: David Hendricks <dhendrix@google.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Support 64-bit MEM BARs wherever possibleCarl-Daniel Hailfinger2011-02-152-24/+133
| | | | | | | | | | | | | | | | | Add more sanity checks for BARs and abort if resources are unreachable. Undecoded resources are reported, but flashrom will proceed anyway just in case the BIOS screwed up the configuration. (The empty CardBus handler is intentional, according to the spec no BARs in PCI config space are used by CardBus.) Found while working on a driver for the Angelbird PCIe-based SSD which has 64-bit capable MEM BARs. Corresponding to flashrom svn r1261. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Add support for some AMD Am29LV* chipsCarl-Daniel Hailfinger2011-02-052-0/+248
| | | | | | | | | | | | Add support for AMD Am29LV001BB, Am29LV001BT, Am29LV002BB, Am29LV002BT, Am29LV004BB, Am29LV004BT, Am29LV008BB, Am29LV008BT. Thanks to Mark Pustjens for testing the Am29LV001BB. Corresponding to flashrom svn r1260. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Improve debugging for unaligned erase in the flash chip emulatorCarl-Daniel Hailfinger2011-02-041-12/+6
| | | | | | | | | Fix out-of-bounds access for chip erase in the flash chip emulator. Corresponding to flashrom svn r1259. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: David Hendricks <dhendrix@google.com>
* Support for Angelbird Wings PCIe SSD (solid-state drive)Carl-Daniel Hailfinger2011-02-046-1/+235
| | | | | | | | | | | | | | | It uses a Marvell 88SX7042 SATA controller internally which has access to a separate flash chip hosting the option ROM. Thanks to Angelbird Ltd for sponsoring development of this driver! I expect the code to work for that SATA controller even if it is not part of the Angelbird SSD. Corresponding to flashrom svn r1258. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Support Dediprog LEDs on devices with 2 and 3 LEDsStefan Reinauer2011-01-281-87/+90
| | | | | | | Corresponding to flashrom svn r1257. Signed-off-by: Stefan Reinauer <reinauer@google.com> Acked-by: Mathias Krause <mathias.krause@secunet.com>
* Fix sparse warning: Unknown escape %Peter Huewe2011-01-252-2/+2
| | | | | | | | | | | This patch fixes wrong escaping of %. In print.c %%2b is correct instead of \%2b ("%%2b"=%2b=+) In board_enable.c %d is correct instead of \%d. Corresponding to flashrom svn r1256. Signed-off-by: Peter Huewe <peterhuewe@gmx.de> Acked-by: Stefan Reinauer <stepan@coreboot.org>
* Fix sparse warning: Using plain integer as NULL pointerPeter Huewe2011-01-247-27/+27
| | | | | | | | | | | This patch fixes the "using plain integer as NULL pointer" warnings generated by running sparse on the flashrom source. Corresponding to flashrom svn r1255. Signed-off-by: Peter Huewe <peterhuewe@gmx.de> Acked-by: Mathias Krause <mathias.krause@secunet.com> Acked-by: Stefan Reinauer <stepan@coreboot.org>
* Secret knowledge is cool, but public knowledge is betterCarl-Daniel Hailfinger2011-01-201-5/+117
| | | | | | | | | | | | | | | Implement all Dediprog commands found in USB traces, even if their purpose is not yet known. Annotate unknown commands with info about the call sequence they are embedded in and the firmware version of the log. Add a new shutdown command for firmware 5.x (of which Stefan thinks it's "switch the Pass light on" hence it is called late in the game) Corresponding to flashrom svn r1254. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <reinauer@google.com>
* Avoid printing mapped addresses for programmers that do not map flash chipsStefan Reinauer2011-01-191-2/+9
| | | | | | | | | | | | | | Don't print the local memory flash chip address on programmers that don't actually map the flash chip into local memory (like the dediprog) because the value does not make sense there. This version was reworked / rewritten by Mathias Krause to have less "impact" Corresponding to flashrom svn r1253. Signed-off-by: Stefan Reinauer <reinauer@google.com> Acked-by: Mathias Krause <mathias.krause@secunet.com>
* Convince compilers to put constant data into the .rodata sectionMathias Krause2011-01-178-26/+26
| | | | | | | | | | | | | | | | This patch reduces the stack usage by declaring 'const' stack variables as 'static const' so they end up in the .rodata section instead of being copied from there to the stack for every invocation of the corresponding function. As a plus we end up in having a smaller binary as the "copy from .rodata to stack" code isn't emitted by the compiler any more (roughly -100 bytes). Corresponding to flashrom svn r1252. Signed-off-by: Mathias Krause <mathias.krause@secunet.com> Acked-by: Stefan Reinauer <stepan@coreboot.org>
* The AT26DF081A requires the Write Enable Latch (WLE) to be set for ↵Mathias Krause2011-01-171-2/+3
| | | | | | | | | | | | | write/erase operations Also bit 5 is the Erase/Program Error (EPE) bit, so has nothing to do with the block protection. Ignore it when testing for block protections. Corresponding to flashrom svn r1251. Signed-off-by: Mathias Krause <mathias.krause@secunet.com> Tested-by: Mathias Krause <mathias.krause@secunet.com> Acked-by: Stefan Reinauer <stepan@coreboot.org>
* Fix decoding of SB600 LPC ROM protection registersMathias Krause2011-01-011-6/+6
| | | | | | | | | | The address part was using a bit of the size, the size was missing the upper bit, was off by 1023 bytes and included the protection bits. Corresponding to flashrom svn r1250. Signed-off-by: Mathias Krause <mathias.krause@secunet.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Compilation fix for djgppIdwer Vollering2010-12-261-3/+3
| | | | | | | | | | | | This corrects a djgpp build error, seen with r1232 and later. pcidev.c:210: error: conflicting types for 'rpci_write_long' programmer.h:226: error: previous declaration of 'rpci_write_long' was here Corresponding to flashrom svn r1249. Signed-off-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
* Enable unlocking (erasing/writing) W39V040FB chipsIdwer Vollering2010-12-263-0/+12
| | | | | | | | | | Add code for the unlocking (erasing/writing) of Winbond W39V040FB chips, enabling erasing/writing this type of chip. Corresponding to flashrom svn r1248. Signed-off-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
* Mark MX25L3205, W25Q80, W25Q32 and W25Q64 as fully testedDavid Hendricks2010-12-131-4/+4
| | | | | | | Signed-off-by: David Hendricks <dhendrix@google.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> Corresponding to flashrom svn r1247.
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