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* Add 28 flash chips of the MX29 series to the flashrom ID table and support ↵Carl-Daniel Hailfinger2008-12-102-0/+34
| | | | | | | | | | | the MX29LV040C MX29LV040C probe and read support tested by khetzal on IRC. Corresponding to flashrom svn r366 and coreboot v2 svn r3809. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Kill obsolete and misplaced commentCarl-Daniel Hailfinger2008-12-081-1/+1
| | | | | | | Corresponding to flashrom svn r365 and coreboot v2 svn r3806. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Generates OPCODES struct from the ICH7/ICH9/VIA chipset if its SPI ↵FENG yu ning2008-12-083-0/+145
| | | | | | | | | configuration is locked down Corresponding to flashrom svn r364 and coreboot v2 svn r3805. Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Breaks chip info into multiple linesFENG yu ning2008-12-081-160/+937
| | | | | | | Corresponding to flashrom svn r363 and coreboot v2 svn r3804. Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Display test status in -L chip listingPeter Stuge2008-12-061-4/+51
| | | | | | | | | | | | | | | | | | Looks like this: Supported flash chips: Tested OK operations: Known BAD operations: AMD Am29F002(N)BB AMD Am29F002(N)BT PROBE READ ERASE WRITE AMD Am29F016D AMD Am29F040B PROBE READ ERASE WRITE AMD Am29LV040B Atmel AT45CS1282 READ Corresponding to flashrom svn r362 and coreboot v2 svn r3803. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add AMD SB700 flash enableNiels Ole Salscheider2008-12-051-0/+1
| | | | | | | | | | | This patch adds SB700 support to flashrom. The code for enabling the flash rom is the same as for SB600. It was tested (read, write, verify) with an ASUS M3A-H/HDMI which contains a Macronix MX25L8005. Corresponding to flashrom svn r361 and coreboot v2 svn r3799. Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de> Acked-by: Peter Stuge <peter@stuge.se>
* Fix compilation of r3797 with gcc-4.3.2Peter Stuge2008-12-051-1/+1
| | | | | | | | | Thanks to Niels Ole Salscheider for the problem report. Corresponding to flashrom svn r360 and coreboot v2 svn r3798. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Check if erase succeeds and exit with error on failurePeter Stuge2008-12-051-4/+17
| | | | | | | | | Flashrom used to exit 0 even if erase failed. Not anymore. Corresponding to flashrom svn r359 and coreboot v2 svn r3797. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Add RDID/REMS IDs for the following flash chipsCarl-Daniel Hailfinger2008-12-041-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SST_25VF512A_REMS SST_25VF010_REMS SST_25VF020_REMS SST_25VF040_REMS SST_25VF040B_REMS SST_25VF080_REMS SST_25VF080B_REMS SST_25VF032B_REMS SST_26VF016 SST_26VF032 W_25X16 W_25X32 W_25X64 Straight from the data sheets. The REMS IDs help in case the RDID opcode is unavailable (due to opcode lockdown) or unsupported by the chip. Some day, we need to pair probe functions together with IDs. Multiple pairs can exist per chip and duplicating chip definitions does not really make sense. Corresponding to flashrom svn r358 and coreboot v2 svn r3793. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Gcc thinks base could be used uninitialized, so shut it upPeter Stuge2008-12-031-1/+1
| | | | | | | | | Bug from r3791. Corresponding to flashrom svn r357 and coreboot v2 svn r3792. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Fix bug in r3790Peter Stuge2008-12-031-5/+5
| | | | | | | | | | If flashbase was set before probe_flash() it would only ever be used once, for the very first flash chip probe. Corresponding to flashrom svn r356 and coreboot v2 svn r3791. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Replace #ifdefs for sc520 systems by run time probingStefan Reinauer2008-12-034-11/+64
| | | | | | | | | | Fixes #109 Corresponding to flashrom svn r355 and coreboot v2 svn r3790. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Copyright update by Jason Wang for freshly written sb600 codeJason Wang2008-11-291-3/+3
| | | | | | | | Corresponding to flashrom svn r354 and coreboot v2 svn r3782. Signed-off-by: Jason Wang <Qingpei.wang@amd.com> Reviewed-by: Joe, Bao <Zheng.Bao@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Declare special commands to support the Atmel AT25F512ACarl-Daniel Hailfinger2008-11-281-0/+5
| | | | | | | Corresponding to flashrom svn r353 and coreboot v2 svn r3781. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Do not indicate known-bad functions as untestedCarl-Daniel Hailfinger2008-11-282-6/+11
| | | | | | | | | | | If a chip has any TEST_BAD_* flag set, we don't even list the unsupported functions, giving the user the impression that the unsupported functions are tested. Corresponding to flashrom svn r352 and coreboot v2 svn r3780. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se>
* Add support for the AMD/ATI SB600 southbridge SPI functionalityJason Wang2008-11-287-19/+245
| | | | | | | | | | This has been tested by Uwe Hermann on an RS690/SB600 board. Corresponding to flashrom svn r351 and coreboot v2 svn r3779. Signed-off-by: Jason Wang <Qingpei.Wang@amd.com> Reviewed-by: Joe Bao <zheng.bao@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add SST25VF080B flash chip supportJason Wang2008-11-281-0/+1
| | | | | | | | | | | This is the first chip which uses the infrastructure for alternative erase commands, namely spi_chip_erase_60_c7(). Corresponding to flashrom svn r350 and coreboot v2 svn r3776. Signed-off-by: Jason Wang <Qingpei.Wang@amd.com> Reviewed-by: Joe Bao <zheng.bao@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Flashrom already has the following probe functionsCarl-Daniel Hailfinger2008-11-283-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | - probe_spi_rdid with opcode 0x9f, usually 3 bytes ID - probe_spi_res with opcode 0xab, usually 1 byte ID We are missing the following probe function: - probe_spi_rems with opcode 0x90, usually 2 bytes ID RDID provides best specifity (manufacturer, device class and device) and RES is supported by quite a few old chips. However, RES only returns one byte and there are multiple flash chips with different sizes on the market and all of them have the same RES ID. REMS is from the same age as RES, but it provides a manufacturer and a device ID. It is therefore on par with the probing for parallel flash chips and specific enough. The order in which chips should be detected is as follows: 1. RDID 2. REMS 3. RES Corresponding to flashrom svn r349 and coreboot v2 svn r3775. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se>
* Try RES even if RDID failsCarl-Daniel Hailfinger2008-11-271-7/+5
| | | | | | | | | | | | | | | | | | | The existing check in probe_spi_res() was right for SPI controllers which support all commands, but may not exist. For controllers which support only a subset of commands, it will fail in unexpected ways. Even if a command is supported by the controller, it may be unavailable if the controller is locked down. The new logic checks if RDID could be issued and its return values made sense (not 0xff 0xff 0xff). In that case, RES probing is not performed. Otherwise, we try RES. There is one drawback: If RDID returned unexpected values, we don't issue a RES probe. However, in that case we should try to match RDID anyway. Corresponding to flashrom svn r348 and coreboot v2 svn r3774. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: FENG yu ning <fengyuning1984@gmail.com>
* Add support for 32Mbit SPI flash SST25VF032BTero O Peippola2008-11-241-0/+1
| | | | | | | | | | | Tested on gigabyte m57sli. File util/flashrom/flash.h already had correct ID for that part. Corresponding to flashrom svn r347 and coreboot v2 svn r3769. Signed-off-by: Tero O Peippola <xeropp@gmail.com> Acked-by: Peter Stuge <peter@stuge.se>
* ichspi: use spi_nbyte_read() instead of running the opcode directlyCarl-Daniel Hailfinger2008-11-181-9/+5
| | | | | | | | | | | | | | Currently flashrom assumes every vendor BIOS shares our view about which SPI opcodes should be placed in which location. Move to a less optimistic implementation and actually use the generic SPI read functions. They're useful for abstracting exactly this stuff and that makes them the preferred choice. Corresponding to flashrom svn r346 and coreboot v2 svn r3758. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Check for failed SPI command executionCarl-Daniel Hailfinger2008-11-182-21/+71
| | | | | | | | | | | | | | | | | | | | | | | Although SPI itself does not have a mechanism to signal command failure, the SPI host may be unable to send a given command over the wire due to security or hardware limitations. The current code ignores these mechanisms completely and simply assumes almost every command succeeds. Complain if SPI command execution fails. Since locked down Intel chipsets (like the one we had problems with earlier) only allow a small subset of commands, find the common subset of commands between the chipset and the ROM in the chip erase case. That is accomplished by the new spi_chip_erase_60_c7() which can be used for chips supporting both 0x60 and 0xc7 chip erase commands. Both parts of the patch address problems seen in the real world. The increased verbosity for the error case will help us diagnose and address problems better. Corresponding to flashrom svn r345 and coreboot v2 svn r3757. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Otherwise: Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Implement read support for the following Atmel chipsCarl-Daniel Hailfinger2008-11-181-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | AT25DF021 AT25DF041A AT25DF081 AT25DF161 AT25DF321A AT25DF641 AT25F512B AT25FS010 AT25FS040 AT26DF041 AT26DF081A AT26DF161 AT26DF161A AT26DF321 AT26F004 I double-checked the data sheets and am confident this will work. Corresponding to flashrom svn r344 and coreboot v2 svn r3756. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* SST39VF020 TEST_OK_ PROBE READ ERASE WRITEMart Raudsepp2008-11-171-1/+1
| | | | | | | | | Tested fully on a ThinCan DBE61A Corresponding to flashrom svn r343 and coreboot v2 svn r3755. Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
* The AT25 and AT26 series SPI chips from Atmel are plain EEPROMsCarl-Daniel Hailfinger2008-11-153-2/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AT45 series SPI chips are DataFlash EEPROMs which means they have odd (non-power-of-two) sector sizes, but some of the DataFlash chips can be configured or ordered with power-of-two sector sizes. Add probe support for the following Atmel SPI chips: AT25DF021 AT25DF041A AT25DF081 AT25DF161 AT25DF321A AT25DF641 AT25F512B AT25FS010 AT25FS040 AT26DF041 AT26DF081A AT26DF161 AT26DF161A AT26DF321 AT26F004 AT45CS1282 AT45DB011D AT45DB021D AT45DB041D AT45DB081D AT45DB161D AT45DB321C AT45DB321D AT45DB642D Add an explanation why the following chips can't be probed: AT45BR3214B AT45D011 AT45D021A AT45D041A AT45D081A AT45D161 AT45DB011 AT45DB011B AT45DB021A AT45DB021B AT45DB041A AT45DB081A AT45DB161 AT45DB161B AT45DB321 AT45DB321B AT45DB642 Add the ID, but no probing function for this chip: AT25F512A Corresponding to flashrom svn r342 and coreboot v2 svn r3754. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Tested-by: Andriy Gapon <avg@icyb.net.ua> Acked-by: Myles Watson <mylesgw@gmail.com>
* SST39SF040 TEST_OK_ PROBE READ ERASE WRITEPeter Stuge2008-11-081-1/+1
| | | | | | | | | Per report from Mario Rogen. Thanks! Corresponding to flashrom svn r341 and coreboot v2 svn r3736. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Mark ST M25P16 as fully testedCarl-Daniel Hailfinger2008-11-051-1/+1
| | | | | | | | | This has been confirmed by Stéphan Guilloux. Corresponding to flashrom svn r340 and coreboot v2 svn r3731. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add support for 8 new chips and fix up 2 existing chips as wellCarl-Daniel Hailfinger2008-11-042-12/+18
| | | | | | | | | | | | | | | | | | | | | | | | | Replace age-old TODO comments with real explanations. Fixed chips: Fujitsu MBM29F400TC (ID definition) Macronix MX29F002T (chip name) New chips: Fujitsu MBM29F004BC Fujitsu MBM29F004TC Fujitsu MBM29F400BC Macronix MX25L512 Macronix MX25L1005 Macronix MX25L2005 Macronix MX25L6405 Macronix MX29F002B Straight from the data sheets, compile tested only. Corresponding to flashrom svn r339 and coreboot v2 svn r3730. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Dump ICH8/ICH9/ICH10 SPI registersCarl-Daniel Hailfinger2008-11-031-5/+45
| | | | | | | | | This helps a lot if we have to track down configuration weirdnesses. Corresponding to flashrom svn r338 and coreboot v2 svn r3723. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Add additional SPI sector erase and chip erase command functionsCarl-Daniel Hailfinger2008-11-033-16/+42
| | | | | | | | | | | | | | | | | | | Not all chips support all commands, so allow the implementer to select the matching function. Fix a layering violation in ICH SPI code to be less bad. Still not perfect, but the new code is shorter, more generic and architecturally more sound. TODO (in a separate patch): - move the generic sector erase code to spi.c - decide which erase command to use based on info about the chip - create a generic spi_erase_all_sectors function which calls the generic sector erase function Thanks to Stefan for reviewing and commenting. Corresponding to flashrom svn r337 and coreboot v2 svn r3722. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Drop nr/opcode_index parameter from run_opcode and search the opmenu for the ↵Stefan Reinauer2008-11-021-15/+45
| | | | | | | | | | | | opcode instead This is slightly slower (ha, ha), but works on boards with a locked opmenu. Tested on ICH7 and works. Corresponding to flashrom svn r336 and coreboot v2 svn r3721. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add support for the ST M50FW002 chipCarl-Daniel Hailfinger2008-11-022-0/+2
| | | | | | | | | | | Identification only, erase/write are not implemented. Corresponding to flashrom svn r335 and coreboot v2 svn r3717. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> tested and Acked-by: Elia Yehuda <z4ziggy@gmail.com>
* Mark two more chips as fully testedUwe Hermann2008-10-301-2/+2
| | | | | | | | | | | | - SST SST39SF010A - Winbond W29C011 Tested by me on actual hardware, all operations. Corresponding to flashrom svn r334 and coreboot v2 svn r3708. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Flashrom support for some Numonyx parts (M25PE)Stefan Reinauer2008-10-293-0/+29
| | | | | | | | | Using block erase d8 as discussed with Peter Stuge Corresponding to flashrom svn r333 and coreboot v2 svn r3707. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Enable SPI boot flash support on EP80579, which has the ICH7 register setEd Swierk2008-10-291-1/+1
| | | | | | | Corresponding to flashrom svn r332 and coreboot v2 svn r3706. Signed-off-by: Ed Swierk <eswierk@aristanetworks.com> Acked-by: Ed Swierk <eswierk@aristanetworks.com>
* Mark Winbond W39V040FA (512 KB) as fully supportedUwe Hermann2008-10-281-1/+1
| | | | | | | | | | Tested by Martin Stecklum <stecky@gmx.net> (both write and erase). The tests were done on an MSI MS-7065 board, so that's supported now too. Corresponding to flashrom svn r331 and coreboot v2 svn r3697. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add support for the Intel 82371MX (MPIIX) southbridgeUwe Hermann2008-10-281-3/+5
| | | | | | | | | | Untested, but should work just as well as the other *PIIX* southbridges according to the datasheets. Corresponding to flashrom svn r330 and coreboot v2 svn r3696. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add support for the Intel 82371FB PIIX and 82371SB (PIIX3) southbridgesUwe Hermann2008-10-261-1/+7
| | | | | | | | | Tested on PIIX3 hardware. Corresponding to flashrom svn r329 and coreboot v2 svn r3694. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey.osgood@gmail.com>
* Add support for the VIA VT82C586A/B chipset, improve documentationUwe Hermann2008-10-251-1/+4
| | | | | | | Corresponding to flashrom svn r328 and coreboot v2 svn r3693. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Reduce serial output, otherwise flashing will fail very oftenUwe Hermann2008-10-211-2/+4
| | | | | | | | | This has been tested on hardware by me. Corresponding to flashrom svn r327 and coreboot v2 svn r3682. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Coding-style fixes for flashrom, partly indent-aidedUwe Hermann2008-10-1813-233/+284
| | | | | | | Corresponding to flashrom svn r326 and coreboot v2 svn r3669. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Allow the SiS 620 chipset to detect and read at least 256kb chipsUrja Rannikko2008-10-181-0/+11
| | | | | | | | | | Based on the 5595 datasheet and uniflash 1.40 sources, only looking for info about SiS620. Corresponding to flashrom svn r325 and coreboot v2 svn r3668. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Acked-by: Peter Stuge <peter@stuge.se>
* SB600 has four write once LPC ROM protect areasMarc Jones2008-10-151-0/+21
| | | | | | | | | | | | It is not possible to write enable that area once the register is set so print a warning. Corresponding to flashrom svn r324 and coreboot v2 svn r3659. Signed-off-by: Marc Jones <marcj.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add ICH10 supportCarl-Daniel Hailfinger2008-10-101-0/+10
| | | | | | | | | | The ICH9 and ICH10 data sheets are identical regarding FWH/SPI flash interfaces, so this just adds the required PCI IDs. Corresponding to flashrom svn r323 and coreboot v2 svn r3648. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se>
* Check that a filename was specified also when using force readPeter Stuge2008-10-101-0/+4
| | | | | | | Corresponding to flashrom svn r322 and coreboot v2 svn r3647. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Support for AM29F002(N)B[BT]Mats Erik Andersson2008-10-072-1/+5
| | | | | | | | | | | | | Fully tested on AM29F002NBT. Probing, reading, and erasing use the Jedec-routines, whereas writing resort to the recent write_en29f002a(), since also these chips use a byte wise algorithm. Corresponding to flashrom svn r321 and coreboot v2 svn r3639. Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* This patch fixes support for the AT49F002N(T) chip in the flashrom toolTim ter Laak2008-09-301-2/+2
| | | | | | | | | | | | | | It replaces the write function to one based on write_byte_program_jedec() instead of write_page_write_jedec(), as this part does not support page programming. I have verified the NT variant to fully work now, and adjusted the test status accordingly. The N variant *should* also work with this patch, but remains untested. Corresponding to flashrom svn r320 and coreboot v2 svn r3619. Signed-off-by: Tim ter Laak <timl@scintilla.utwente.nl> Acked-by: Peter Stuge <peter@stuge.se>
* ST M29F040B status TEST_OK_ PROBE READ ERASE WRITEPeter Stuge2008-09-301-1/+1
| | | | | | | | | Per report from Daniel Lindenaar. Thanks! Corresponding to flashrom svn r319 and coreboot v2 svn r3618. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Fix typo in r3615 (TEST_PREW -> TEST_OK_PREW)Peter Stuge2008-09-291-1/+1
| | | | | | | Corresponding to flashrom svn r318 and coreboot v2 svn r3616. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Mark the SyncMOS S29C51002T as workingUwe Hermann2008-09-291-1/+1
| | | | | | | | | All operations tested by me on hardware. Corresponding to flashrom svn r317 and coreboot v2 svn r3615. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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