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* edi: Print debug info like others while probing for ENE chipsMike Banon2018-02-111-2/+8
| | | | | | | | | | | | | | | Instead of just "Probing for ENE KB9012 (EDI), 128 kB:", lets print some debug info - like it is currently being printed for other chips: Probing for ENE KB9012 (EDI), 128 kB: edi_chip_probe: hwversion 0xc3, ediid 0x04 Found ENE flash chip "KB9012 (EDI)" (128 kB, SPI) on ch341a_spi. Change-Id: Id8e62bc9f6785b4bf0be0aaf0f74c8120d77c0d4 Signed-off-by: Mike Banon <mikebdp2@gmail.com> Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/23261 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* edi: Add dummy read to ensure proper detection of ENE chipsPaul Kocialkowski2018-02-111-0/+12
| | | | | | | | | | | | | | | | ENE chips enable EDI by detecting a clock frequency between 1 MHz and 8 MHz. In many cases, the chip won't be able to both detect the clock signal and serve the associated request at the same time. Thus, a dummy read has to be added to ensure that EDI is enabled and operational starting from the next request. Change-Id: I69ee71674649cd8ba4fc635f889cb39a1cd204b9 Signed-off-by: Mike Banon <mikebdp2@gmail.com> Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/23260 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add support for the ENE Embedded Debug Interface EDI and KB9012 ECPaul Kocialkowski2018-02-117-2/+611
| | | | | | | | | | | | | | | | | | | | | | | | The ENE Embedded Debug Interface (EDI) is a SPI-based interface for accessing the memory of ENE embedded controllers. The ENE KB9012 EC is an embedded controller found on various laptops such as the Lenovo G505s. It features a 8051 microcontroller and has 128 KiB of internal storage for program data. EDI can be accessed on the KB9012 through pins 59-62 (CS-CLK-MOSI-MISO) when flash direct access is not in use. Some firmwares disable EDI at runtime so it might be necessary to ground pin 42 to reset the 8051 microcontroller before accessing the KB9012 via EDI. The example of flashing KB9012 at Lenovo G505S laptop could be found here: http://dangerousprototypes.com/docs/Flashing_KB9012_with_Bus_Pirate Change-Id: Ib8b2eb2feeef5c337d725d15ebf994a299897854 Signed-off-by: Mike Banon <mikebdp2@gmail.com> Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/23259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Add support for selecting the erased bit value with a flagPaul Kocialkowski2018-02-112-15/+26
| | | | | | | | | | | | Most flash chips are erased to ones and programmed to zeros. However, some other chips, such as the ENE KB9012 internal flash, work the opposite way. Change-Id: Ia7b0de8568e31f9bf263ba0ad6b051e837477b6b Signed-off-by: Mike Banon <mikebdp2@gmail.com> Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/23258 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add a SPI command class to `struct flashchip`Mike Banon2018-02-112-0/+14
| | | | | | | | | | | | | | | | | | | | By default, we want to probe for SPI25 chips only. Other SPI use cases, like the ENE/EDI protocol, might use commands that can confuse these common chips. Now, flashrom will probe for a chip only if one of these conditions is true: 1) no chip has been specified AND the chip uses the SPI25 commands 2) this chip has been specified by -c | --chip <chipname> The CLI can later be extended to probe for a specific class of chips. Change-Id: I89a53ccaef2791a2ac32904d7ab813da7478a6f0 Signed-off-by: Mike Banon <mikebdp2@gmail.com> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/23262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
* chipset_enable: Mark VX855 as testedLubomir Rintel2018-01-261-1/+1
| | | | | | | | | | | | I can confirm a successful reading and writing of SST49LF080A (LPC) on a Wyse Cx0 Thin Client (Phoenix BIOS 1.0G). Change-Id: I8f48b49ccb760f69d676ec6cbb233e532b12fbe8 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/23158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
* buspirate_spi: Add support for variable serial speedsShawn Anastasio2018-01-263-11/+134
| | | | | | | | | | | | | | | | | | | | | | | | This patch sets the default baud rate for communication between the host device and the Bus Pirate for hardware versions 3.0 and greater to 2M baud. It also introduces the ability to manually set the baud rate via the added 'serialspeed' programmer parameter. This is done in two parts. Firstly, the requested serial speed is looked up in a table to determine the appropriate clock divisor and the divisor is sent to the bus pirate. Then, the system's baud rate for the selected serial port is set using serial.c's 'serialport_config'. This function's prototype had to be added to programmer.h. In testing, using the 2M baud rate was able to significantly decrease flash times (down from 20+ minutes to less than 2 minutes for an 8MB flash). Change-Id: I3706f17a94fdf056063f2ad4a5f0a219665cdcbf Signed-off-by: Shawn Anastasio <shawnanastasio@yahoo.com> Reviewed-on: https://review.coreboot.org/23057 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Fix the documentation and DOS portRudolf Marek2018-01-062-26/+53
| | | | | | | | | | | | Update the DOS cross-compile documentation, and workaround issue with valloc() with the latest DJGPP. Change-Id: I909c5635aec5076440d2fde73d943f8ad10b8051 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: https://review.coreboot.org/23039 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* chipset_enable: Mark VX900 as testedLubomir Rintel2018-01-021-1/+1
| | | | | | | | | | | I can confirm a successful reading and writing of MX25L8005 (SPI) on a HP t5550 Thin Client (AMI BIOS 786R9 v1.04). Change-Id: I190253b0c1920747b710ed7155e78191cce139eb Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/23030 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vt_vx: check whether the chipset's MMIO range is configuredLubomir Rintel2018-01-021-0/+8
| | | | | | | | | | | | Avoid attempting to read the SPI bases from the location 0x00000000, all zeroes mean that the chipset's MMIO area is not enabled. Change-Id: I5d3a1ba695153e854e0979ae634f8ed97e6b6293 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/23029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* flashchips: Revise all 4BA chipsNico Huber2018-01-022-16/+50
| | | | | | | | | | | | | | | | Advertise all 4BA features that are currently supported by flashrom, plus add a new feature flag for the 4BA fast-read instruction. Also, list all supported 3BA and 4BA erase-block functions. As this adds a lot of new code paths that could be taken for these chips, mark them all as untested again. Change-Id: I0598496ee7058e3b170684d366f58e4014e0e871 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22423 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* spi25: Revise decision when to enter/exit 4BA modeNico Huber2018-01-025-47/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of arbitrarily deciding whether to enter 4BA mode in the flash chip's declaration, advertise that entering 4BA mode is supported and only enter it if the SPI master supports 4-byte addresses. If not, exit 4BA mode (the chip might be in 4BA mode after reset). If we can't assure the state of 4BA mode, we bail out to simplify the code (we'd have to ensure that we don't run any instructions that can usually be switched to 4BA mode otherwise). Two new feature flags are introduced: * FEATURE_4BA_ENTER: Can enter/exit 4BA mode with instructions 0xb7/0xe9 w/o WREN. * FEATURE_4BA_ENTER_WREN Can enter/exit 4BA mode with instructions 0xb7/0xe9 after WREN. FEATURE_4BA_SUPPORT is dropped, it's completely implicit now. Also, draw the with/without WREN distinction into the enter/exit functions to reduce code redundancy. Change-Id: I877fe817f801fc54bd0ee2ce4e3ead324cbb3673 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22422 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* spi_master: Introduce SPI_MASTER_4BA feature flagNico Huber2018-01-029-5/+30
| | | | | | | | | | | | | | | Add a feature flag SPI_MASTER_4BA to `struct spi_master` that advertises programmer-side support for 4-byte addresses in generic commands (and read/write commands if the master uses the default implementations). Set it for all masters that handle commands address-agnostic. Don't prefer native 4BA instructions if the master doesn't support them. Change-Id: Ife66e3fc49b9716f9c99cad957095b528135ec2c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* spi: Move ICH BBAR quirk out of the wayNico Huber2017-12-285-85/+29
| | | | | | | | | | | | | | | | | | | | | Get rid of the layering violations around ICH's BBAR. Move all the weird address handling into (surprise, surprise) `ichspi.c`. Might fix writes for the `BBAR != 0` case by accident. Background: Some ICHs have a BBAR (BIOS Base Address Configuration Register) that, if set, limits the valid address range to [BBAR, 2^24). Current code lifted addresses for REMS, RES and READ operations by BBAR, now we do it for all addresses in ichspi. Special care has to be taken if the BBAR is not aligned by the flash chip's size. In this case, the lower part of the chip (from BBAR aligned down, up to BBAR) is inacces- sible (this seems to be the original intend behind BBAR) and has to be left out in the address offset calculation. Change-Id: Icbac513c5339e8aff624870252133284ef85ab73 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22396 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25: Merge remainder of spi4ba inNico Huber2017-12-287-466/+119
| | | | | | | | Change-Id: If581e24347e45cbb27002ea99ffd70e334c110cf Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22388 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi4ba: Drop now obsolete, redundant functionsNico Huber2017-12-281-651/+0
| | | | | | | | Change-Id: I1d04448fd1acbfc37b8e17288f497a4292dfd6d6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22387 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25: Remove now obsolete `four_bytes_addr_funcs` pathNico Huber2017-12-284-76/+22
| | | | | | | | Change-Id: Idb7c576cb159630da2268813388b497cb5f46b43 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22386 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25: Enable native 4BA read and write using feature bitsNico Huber2017-12-283-21/+28
| | | | | | | | | | | Prefer the native 4BA instruction when they are supported. In this case, override our logic to decide to use a 4BA address. Change-Id: I2f6817ca198bf923671a7aa67e956e5477d71848 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22385 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25: Integrate 4BA supportNico Huber2017-12-285-9/+57
| | | | | | | | | | | | | | | | | | Allow 4-byte addresses for instructions usually used with 3-byte addresses. Decide in which way the 4th byte will be communicated based on the state of the chip (i.e. have we enabled 4BA mode) and a new feature bit for an extended address register. If we are not in 4BA mode and no extended address register is available or the write to it fails, bail out. We cache the state of 4BA mode and the extended address register in the flashctx. Change-Id: I644600beaab9a571b97b67f7516abe571d3460c1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22384 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25: Use common code for nbyte read/write and block eraseNico Huber2017-12-283-429/+105
| | | | | | | | | | | | | | | | | | Introduce spi_prepare_address() and spi_write_cmd() and use them in nbyte_program, nbyte_read and block-erase procedures. The former abstracts over the address part of a SPI command to make it exten- sible for 4-byte adressing. spi_write_cmd() implements a WREN + write operation with address and optionally up to 256 bytes of data. It provides a common path to reduce overall redundancy. Also, reduce the polling delay in spi_block_erase_c4() from 500s to 500ms as the comment suggests. Change-Id: Ibc1ae48acbfbd427a30bcd64bdc080dc3dc20503 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* spi25: Introduce spi_simple_write_cmd()Nico Huber2017-12-282-95/+39
| | | | | | | | | | | | spi_simple_write_cmd() executes WREN plus a single byte write and polls WIP afterwards. It's used to replace current spi_erase_chip_*() imple- mentations. Change-Id: Ib244356fa471e15863b52e6037899d19113cb4a9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* internal: Only build on x86 and mipselNico Huber2017-12-192-38/+12
| | | | | | | | | | | | | internal_init() explicitly fails on everything but x86 and mipsel. Instead, we can just never build the internal programmer on other architectures and drop a lot of #if boilerplate. Change-Id: I672ddab0415df3baa49ff39a1c9db1b41d8143a4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* Move endianness definitions and provide it inside MakefileNico Huber2017-12-194-83/+89
| | | | | | | | | | | | | | Add an `endiantest.c` similar to `archtest.c` to provide the endianness inside the Makefile. The __FLASHROM_(LITTLE|BIG)_ENDIAN__ definitions had to move from `hwaccess.h` into `platform.h`, therefor. This will be used to decide whether to build the internal programmer in a follow- up. Change-Id: I55dcf5a88da48f885cda9ad89ab87395d895a891 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* ichspi: Fix 100 series PCH (Skylake) supportNico Huber2017-12-191-1/+1
| | | | | | | | | | | | | | Pretty subtle missing `else` made flashrom treat Skylake like older chipsets. Change-Id: I14bf578964124d4677cb5dfca01c9d1b0d279c9c Signed-off-by: Nico Huber <nico.h@gmx.de> Reported-by: Youness Alaoui <kakaroto@kakaroto.homelinux.net> Reviewed-on: https://review.coreboot.org/22832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* flashchips: Add ISSI IS25LP128 and IS25WP128David Hendricks2017-12-112-0/+85
| | | | | | | | | | | | IS25LP128 is the 3.3V variant, IS25WP128 is the 1.8V variant. Tested read, erase, and write using Dediprog SF600 on each. Change-Id: Ia1c7a9a950043c30b7525196e03ee394689e89a5 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/22784 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Do not stop probing for flashchips after map_flash() failedMartin Schiller2017-12-111-1/+1
| | | | | | | | | | | | | | | Instead, continue probing the next chip. This fixes the problem that flashrom aborts probing for flashchips if one big flashchip (e.g. 32M/64M) can't be mapped because of activated CONFIG_STRICT_DEVMEM kernel option. Change-Id: Iaecfb6d30a5152c8c4b5d2804efacac85fc615f9 Signed-off-by: Martin Schiller <ms@dev.tdt.de> Reviewed-on: https://review.coreboot.org/22685 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Mark W25Q128.W as testedDavid Hendricks2017-12-101-1/+1
| | | | | | | | | | Tested read, erase, and write using W25Q128FWSIG and Dediprog SF600. Change-Id: Id0ef331ad3b3a8ab05a9472f3053f76c0789b1f9 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/22790 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add MX25L6473FNico Huber2017-12-091-1/+1
| | | | | | | | | | Just another chip sharing the same ID. Tested by somebody on IRC. Change-Id: Ibea956e48e10fda91930b65b3bf3b3ae4ad13f63 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* internal: Fix warnings about unused constantsNico Huber2017-12-091-0/+4
| | | | | | | | | | | | By adding more #if guards, fix warnings about unused constants that are enabled by default in newer GCC versions. Change-Id: Ib3b6d7c0c2fadc4faeab971673bfadb1a6d25919 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* README: Update packaging section for Git repositoriesNico Huber2017-12-011-8/+10
| | | | | | | | Change-Id: I8d9c56be8c1381b175ce7695c53f31b1767d9d17 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* chipset_enable: Mark SiS 630 as tested OKNico Huber2017-11-211-1/+1
| | | | | | | | | | | | | Tested on an Elitegroup P6STMT with an SST39SF020A parallel flash [1]. [1] https://mail.coreboot.org/pipermail/flashrom/2017-November/015193.html Change-Id: If8cc2af262e392bfba326a62c1a48c658c7d6ce8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* linux_spi: Dynamically detect max buffer sizeKeno Fischer2017-11-161-7/+45
| | | | | | | | | | | Read max buffer size from sysfs if available. Change-Id: Ic541e548ced8488f074d388f1c92174cad123064 Signed-off-by: Keno Fischer <keno@juliacomputing.com> Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/22441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ichspi: Disable software sequencing by default for SkylakeNico Huber2017-11-051-0/+5
| | | | | | | | | | | | | | | Skylake is a mess, especially with coreboot. We have now a present and configured software sequencing interface with SCGO supposedly being readonly (Apollo Lake has that feature and a strap documented, Skylake behaviour might be the same). As we can't easily check if it's read- only, just enable hardware sequencing by default (even if the software sequencing interface seems usable). Change-Id: I8a13fb9c3ca679b3f7d39ad1dc56d5efdc80045b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/22274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* spi25_statusreg: Return defined value on failed RDSRNico Huber2017-11-051-1/+4
| | | | | | | | | | | The interface of spi_read_status_register() is broken and can't return errors. Let's not return random stack data at least. Change-Id: I714b20001a5443bba665c2e0061ca14069777581 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* ichspi: Fix software sequencing for SkylakeNico Huber2017-11-031-2/+2
| | | | | | | | | | | Two occurences of ICH9_REG_OPMENU were overlooked and not replaced, rendering the software sequencing unusable on Skylake. Change-Id: I16eebcf37ab8ba39b02f33135535552e380b0b92 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/22273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* Fix standalone ich_descriptor_tool compilation with MinGW and DJGPPStefan Tauner2017-11-032-1/+14
| | | | | | | | | | | | | | | | TARGET_OS as well as EXEC_SUFFIX were only set when called via the main makefile and even then __USE_MINGW_ANSI_STDIO was not set for MinGW. While at it, also replace the hardcoded gnu_printf printf format attribute with __MINGW_PRINTF_FORMAT which is set according to __USE_MINGW_ANSI_STDIO respectively. Change-Id: Id146f5ba06a0e510397c6f32a2bd7c819a405a25 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/21838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Use bzip2 when making a tarballDavid Hendricks2017-10-211-2/+2
| | | | | | | | | | | Tarballs on download.flashrom.org are generally packaged using bzip2, so we may as well be internally consistent. Change-Id: Ib9fb1ea6d5994cd0285ce8db9675640fae992773 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/22116 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* fixup! nicintel_eeprom: Support for I210 emulated EEpromNico Huber2017-10-201-2/+7
| | | | | | | | | | Fix is_i210(), add a comment and break an overlong line. Change-Id: I5d3f71e4e0f77cc8793e7f395baf69e1fad930a3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Fix serprog on FreeBSDMichael Zhilin2017-10-191-1/+1
| | | | | | | | | | | | | | | | | | | | Using serprog on FreeBSD to read an SPI flash (MX25L6406) via an Arduino Nano V3 with flashrom hangs after 5 seconds while reading. The problem is that kernel method "ttydisc_rint" ignores some bytes. It happens due to enabled IEXTEN local flag of termios. TTY cuts a few bytes, Arduino reads 11264 bytes, but flashrom gets only 11244 bytes and waits for the remaining 20 bytes. The fix is simple: turn off the IEXTEN local flag. Tested on Arduino Nano V3 + FreeBSD 12-CURRENT. Change-Id: I7aa6a283d523c544d9b8923cd4c622bf08c0fb3f Signed-off-by: Michael Zhilin <mizhka@gmail.com> Reviewed-on: https://review.coreboot.org/21919 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Urja Rannikko <urjaman@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* serial: Support custom baud rates on linuxUrja Rannikko2017-10-194-11/+136
| | | | | | | | | | | The function to do this is contained in custom_baud.c because of broken include stuff. Change-Id: I2a20f9182cb85e7bce5d6654a2caf20e6202b195 Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-on: https://review.coreboot.org/20224 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Move get_layout() from flashrom.c to layout.cdhendrix2017-10-173-8/+10
| | | | | | | | | Change-Id: Ic67cf53abddc0aa905674acbcde717d9aed2f66e Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/21367 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Fix ID of ST M25P05Stefan Tauner2017-10-161-2/+2
| | | | | | | | | | | | | | The (old) ST (now Micron) M25P05 does only support RES for identification. Unfortunately, the vendor datasheet states the same ID as for the M25P10 (0x10) and thus flashrom has treated these two as evil twins in the past. However, real hardware confirmed that the real ID of this chip is 0x05. Change-Id: Idc75f8cb98e7ef0c47c4527cedcc4da3723bd779 Signed-off-by: Serge Vasilugin <vasilugin@yandex.ru> Tested-by: Serge Vasilugin <vasilugin@yandex.ru> Reviewed-on: https://review.coreboot.org/21920 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Initial MX66L51235F supportTimothy Pearson2017-10-152-0/+48
| | | | | | | | Change-Id: I94bee2832469d2df399a09e2f535a107edaec3e7 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/19856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Initial MX25L25635F supportTimothy Pearson2017-10-151-0/+47
| | | | | | | | Change-Id: I292e12d92cdf3961b8d47492a1d5679ff1ea21ce Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/19855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* 4BA: Add Micron N25Q/MT25QL 32MB and 64MB 3V SPI flashEd Swierk2017-10-151-0/+78
| | | | | | | | | | Use direct 4-byte address commands. Change-Id: I3c130c5ecf4bcc7cf3b34257cb5fc3df523ce08b Signed-off-by: Ed Swierk <eswierk@skyportsystems.com> Reviewed-on: https://review.coreboot.org/20511 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 4BA: Allow disabling 4-byte address mode for SPI flashEd Swierk2017-10-153-46/+10
| | | | | | | | | | | | | | | | | | | | This allows us to support flash chips in any of the following configurations, regardless of whether the chip powers up in 3-byte or 4-byte address mode. - standard commands with extended address register (*_4ba_ereg) or direct commands (*_4ba_direct) in 3-byte address mode (.set_4ba = spi_exit_4ba_*) - standard commands (*_4ba) or direct commands (*_4ba_direct) in 4-byte address mode (.set_4ba = spi_enter_4ba_*) - direct commands (*_4ba_direct) in either address mode (.set_4ba = NULL) Change-Id: I0b25309d731426940fc50956b744b681ab599e87 Signed-off-by: Ed Swierk <eswierk@skyportsystems.com> Reviewed-on: https://review.coreboot.org/20510 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 4BA: Add spi_exit_4ba function to switch SPI flash to 3-byte addressingEd Swierk2017-10-153-0/+49
| | | | | | | | Change-Id: I553e7fb5028f35e14a3a81b3fa8903c1b321a223 Signed-off-by: Ed Swierk <eswierk@skyportsystems.com> Reviewed-on: https://review.coreboot.org/20509 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 4BA: Support for new direct-4BA instructions + W25Q256.V updateBoris Baykov2017-10-156-4/+330
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Large flash chips usually support special instructions to work with 4-bytes address directly from 3-bytes addressing mode and without do switching to 4-bytes mode. There are 13h (4BA Read), 12h (4BA Program) and 21h,5Ch,DCh (4BA Erase), correspondingly. However not all these instructions are supported by all large flash chips. Some chips support 13h only, some 13h,12h,21h and DCh, but not 5Ch. This depends on the manufacturer of the chip. This patch provides code to use direct 4-bytes addressing instructions. This code should work but it tested partially only. My W25Q256FV has support for 4BA_Read (13h), but doesn't have support 4BA_Program (12h) and 4BA_Erase instructions. So, direct 4BA program and erase should be tested after. Patched files ------------- chipdrivers.h + added functions declarations for spi4ba.c flash.h + feature definitions added flashchips.c + modified definition of Winbond W25Q256BV/W25Q256FV chips flashrom.c + modified switch to 4-bytes addressing for direct-4BA instructions spi4ba.h + definitions for 4-bytes addressing JEDEC commands + functions declarations from spi4ba.c (same as in chipdrivers.h, just to see) spi4ba.c + functions for read/write/erase directly with 4-bytes address (from any mode) Change-Id: Ib51bcc5de7826b30ad697fcbb9a5152bde2c2ac9 Signed-off-by: Boris Baykov <dev@borisbaykov.com>, Russia, Jan 2014 [clg: ported from https://www.flashrom.org/pipermail/flashrom/2015-January/013198.html ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-on: https://review.coreboot.org/20508 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 4BA: Support for 4-bytes addressing via Extended Address RegisterBoris Baykov2017-10-155-2/+361
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some flash chips data with addresses more than 24-bit field can address may be accessed by using Extended Address Register. The register has 1-byte size and stores high byte of 32-bit address. Then flash can be read from 3-bytes addressing mode with writing high byte of address to this Register. By using this way we have access to full memory of a chip. Some chips may support this method only. This patch provides code use Extended Address Register. Patched files ------------- chipdrivers.h + added functions declarations for spi4ba.c flash.h + feature definitions added flashrom.c + modified switch to 4-bytes addressing to support extended address register spi4ba.h + definitions for 4-bytes addressing JEDEC commands + functions declarations from spi4ba.c (same as in chipdrivers.h, just to see) spi4ba.c + functions for write Extended Address Register + functions for read/write/erase with Extended Address Register Change-Id: I09a8aa11de2ca14901f142c67c83c4fa0def4e27 Signed-off-by: Boris Baykov <dev@borisbaykov.com>, Russia, Jan 2014 [clg: ported from https://www.flashrom.org/pipermail/flashrom/2015-January/013200.html ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-on: https://review.coreboot.org/20507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* 4BA: Winbond W25Q256.V chip (32MB) declaration, 4-bytes addr modeBoris Baykov2017-10-151-0/+48
| | | | | | | | | | | | | | | | | | | | | | Here is the definition of new W25Q256xV chip with new functions pointers for 4-bytes addressing reads and writes. Erase functions pointers are changed in their old places. New feature flags for 4-bytes mode added. Patched files ------------- flashchips.c + added definition for Winbond W25Q256BV/W25Q256FV chips Change-Id: I90226f453f8147ae5ac7dbbef7549ee3bfacc3d6 Signed-off-by: Boris Baykov <dev@borisbaykov.com>, Russia, Jan 2014 [clg: ported from https://www.flashrom.org/pipermail/flashrom/2015-January/013201.html ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-on: https://review.coreboot.org/20506 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 02:44:46 +0000