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* Mark ST M25P16 as fully testedCarl-Daniel Hailfinger2008-11-051-1/+1
| | | | | | | | | This has been confirmed by Stéphan Guilloux. Corresponding to flashrom svn r340 and coreboot v2 svn r3731. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add support for 8 new chips and fix up 2 existing chips as wellCarl-Daniel Hailfinger2008-11-042-12/+18
| | | | | | | | | | | | | | | | | | | | | | | | | Replace age-old TODO comments with real explanations. Fixed chips: Fujitsu MBM29F400TC (ID definition) Macronix MX29F002T (chip name) New chips: Fujitsu MBM29F004BC Fujitsu MBM29F004TC Fujitsu MBM29F400BC Macronix MX25L512 Macronix MX25L1005 Macronix MX25L2005 Macronix MX25L6405 Macronix MX29F002B Straight from the data sheets, compile tested only. Corresponding to flashrom svn r339 and coreboot v2 svn r3730. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Dump ICH8/ICH9/ICH10 SPI registersCarl-Daniel Hailfinger2008-11-031-5/+45
| | | | | | | | | This helps a lot if we have to track down configuration weirdnesses. Corresponding to flashrom svn r338 and coreboot v2 svn r3723. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Add additional SPI sector erase and chip erase command functionsCarl-Daniel Hailfinger2008-11-033-16/+42
| | | | | | | | | | | | | | | | | | | Not all chips support all commands, so allow the implementer to select the matching function. Fix a layering violation in ICH SPI code to be less bad. Still not perfect, but the new code is shorter, more generic and architecturally more sound. TODO (in a separate patch): - move the generic sector erase code to spi.c - decide which erase command to use based on info about the chip - create a generic spi_erase_all_sectors function which calls the generic sector erase function Thanks to Stefan for reviewing and commenting. Corresponding to flashrom svn r337 and coreboot v2 svn r3722. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Drop nr/opcode_index parameter from run_opcode and search the opmenu for the ↵Stefan Reinauer2008-11-021-15/+45
| | | | | | | | | | | | opcode instead This is slightly slower (ha, ha), but works on boards with a locked opmenu. Tested on ICH7 and works. Corresponding to flashrom svn r336 and coreboot v2 svn r3721. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add support for the ST M50FW002 chipCarl-Daniel Hailfinger2008-11-022-0/+2
| | | | | | | | | | | Identification only, erase/write are not implemented. Corresponding to flashrom svn r335 and coreboot v2 svn r3717. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> tested and Acked-by: Elia Yehuda <z4ziggy@gmail.com>
* Mark two more chips as fully testedUwe Hermann2008-10-301-2/+2
| | | | | | | | | | | | - SST SST39SF010A - Winbond W29C011 Tested by me on actual hardware, all operations. Corresponding to flashrom svn r334 and coreboot v2 svn r3708. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Flashrom support for some Numonyx parts (M25PE)Stefan Reinauer2008-10-293-0/+29
| | | | | | | | | Using block erase d8 as discussed with Peter Stuge Corresponding to flashrom svn r333 and coreboot v2 svn r3707. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Enable SPI boot flash support on EP80579, which has the ICH7 register setEd Swierk2008-10-291-1/+1
| | | | | | | Corresponding to flashrom svn r332 and coreboot v2 svn r3706. Signed-off-by: Ed Swierk <eswierk@aristanetworks.com> Acked-by: Ed Swierk <eswierk@aristanetworks.com>
* Mark Winbond W39V040FA (512 KB) as fully supportedUwe Hermann2008-10-281-1/+1
| | | | | | | | | | Tested by Martin Stecklum <stecky@gmx.net> (both write and erase). The tests were done on an MSI MS-7065 board, so that's supported now too. Corresponding to flashrom svn r331 and coreboot v2 svn r3697. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add support for the Intel 82371MX (MPIIX) southbridgeUwe Hermann2008-10-281-3/+5
| | | | | | | | | | Untested, but should work just as well as the other *PIIX* southbridges according to the datasheets. Corresponding to flashrom svn r330 and coreboot v2 svn r3696. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add support for the Intel 82371FB PIIX and 82371SB (PIIX3) southbridgesUwe Hermann2008-10-261-1/+7
| | | | | | | | | Tested on PIIX3 hardware. Corresponding to flashrom svn r329 and coreboot v2 svn r3694. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey.osgood@gmail.com>
* Add support for the VIA VT82C586A/B chipset, improve documentationUwe Hermann2008-10-251-1/+4
| | | | | | | Corresponding to flashrom svn r328 and coreboot v2 svn r3693. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Reduce serial output, otherwise flashing will fail very oftenUwe Hermann2008-10-211-2/+4
| | | | | | | | | This has been tested on hardware by me. Corresponding to flashrom svn r327 and coreboot v2 svn r3682. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Coding-style fixes for flashrom, partly indent-aidedUwe Hermann2008-10-1813-233/+284
| | | | | | | Corresponding to flashrom svn r326 and coreboot v2 svn r3669. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Allow the SiS 620 chipset to detect and read at least 256kb chipsUrja Rannikko2008-10-181-0/+11
| | | | | | | | | | Based on the 5595 datasheet and uniflash 1.40 sources, only looking for info about SiS620. Corresponding to flashrom svn r325 and coreboot v2 svn r3668. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Acked-by: Peter Stuge <peter@stuge.se>
* SB600 has four write once LPC ROM protect areasMarc Jones2008-10-151-0/+21
| | | | | | | | | | | | It is not possible to write enable that area once the register is set so print a warning. Corresponding to flashrom svn r324 and coreboot v2 svn r3659. Signed-off-by: Marc Jones <marcj.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add ICH10 supportCarl-Daniel Hailfinger2008-10-101-0/+10
| | | | | | | | | | The ICH9 and ICH10 data sheets are identical regarding FWH/SPI flash interfaces, so this just adds the required PCI IDs. Corresponding to flashrom svn r323 and coreboot v2 svn r3648. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se>
* Check that a filename was specified also when using force readPeter Stuge2008-10-101-0/+4
| | | | | | | Corresponding to flashrom svn r322 and coreboot v2 svn r3647. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Support for AM29F002(N)B[BT]Mats Erik Andersson2008-10-072-1/+5
| | | | | | | | | | | | | Fully tested on AM29F002NBT. Probing, reading, and erasing use the Jedec-routines, whereas writing resort to the recent write_en29f002a(), since also these chips use a byte wise algorithm. Corresponding to flashrom svn r321 and coreboot v2 svn r3639. Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* This patch fixes support for the AT49F002N(T) chip in the flashrom toolTim ter Laak2008-09-301-2/+2
| | | | | | | | | | | | | | It replaces the write function to one based on write_byte_program_jedec() instead of write_page_write_jedec(), as this part does not support page programming. I have verified the NT variant to fully work now, and adjusted the test status accordingly. The N variant *should* also work with this patch, but remains untested. Corresponding to flashrom svn r320 and coreboot v2 svn r3619. Signed-off-by: Tim ter Laak <timl@scintilla.utwente.nl> Acked-by: Peter Stuge <peter@stuge.se>
* ST M29F040B status TEST_OK_ PROBE READ ERASE WRITEPeter Stuge2008-09-301-1/+1
| | | | | | | | | Per report from Daniel Lindenaar. Thanks! Corresponding to flashrom svn r319 and coreboot v2 svn r3618. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Fix typo in r3615 (TEST_PREW -> TEST_OK_PREW)Peter Stuge2008-09-291-1/+1
| | | | | | | Corresponding to flashrom svn r318 and coreboot v2 svn r3616. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Mark the SyncMOS S29C51002T as workingUwe Hermann2008-09-291-1/+1
| | | | | | | | | All operations tested by me on hardware. Corresponding to flashrom svn r317 and coreboot v2 svn r3615. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Activate proper support for EN29F002(A)(N)[BT]Mats Erik Andersson2008-09-264-10/+54
| | | | | | | | | | | | Fully tested for Probe/Read/Erase/Write on EN29F002NT. Jedec subroutines 'probe_jedec()' and 'erase_chip_jedec()' are still in use, but a tailored 'write_en29f002a()' is needed due to a byte wise writing mechanism for this chip. Corresponding to flashrom svn r316 and coreboot v2 svn r3602. Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Winbond W49V002A TEST_OK_ PROBE READ ERASE WRITEPeter Stuge2008-09-101-1/+1
| | | | | | | | | Per report from Kevin O'Connor. Thanks Kevin! Corresponding to flashrom svn r315 and coreboot v2 svn r3570. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Debug print actual time base calculated by myusec_calibrate_delay()Peter Stuge2008-09-071-1/+7
| | | | | | | Corresponding to flashrom svn r314 and coreboot v2 svn r3569. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Only find "unknown .. SPI chip" if no other chip was foundPeter Stuge2008-09-031-3/+8
| | | | | | | | | | | | | This removes the false positive matches we've been seeing, and also removes the true positive match in case there is more than one flash chip and the 2nd or 3rd are unknown - but I think that case is uncommon enough to warrant the improvement in the common case. Use flashrom -frc forced read if you have the uncommon case, and/or please add the flash chip to the flashchips array. Corresponding to flashrom svn r313 and coreboot v2 svn r3562. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* SST49LF016C TEST_OK_ PROBE READ ERASE WRITEPeter Stuge2008-09-021-1/+1
| | | | | | | | | Per test report from Bari Ari. Thanks! Corresponding to flashrom svn r312 and coreboot v2 svn r3557. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* SST25VF016B TEST_OK_ PROBE READ ERASE WRITEPeter Stuge2008-08-271-1/+1
| | | | | | | | | Per test report from Ward. Corresponding to flashrom svn r311 and coreboot v2 svn r3541. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Recognize the Intel EP80579 LPC flash interfaceEd Swierk2008-08-201-0/+1
| | | | | | | Corresponding to flashrom svn r310 and coreboot v2 svn r3532. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add support for MSI KT4VSean Nelson2008-08-191-0/+47
| | | | | | | | | | The KT4V is autodetected and supports the KT3 Ultra 2 with "-m msi:kt4v" (but is not autodetected, yet). Corresponding to flashrom svn r309 and coreboot v2 svn r3528. Signed-off-by: Sean Nelson <snelson@nmt.edu> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Fix error -EINVAL on mmap()Segher Boessenkool2008-08-121-8/+8
| | | | | | | | | | | | | Don't calculate "flash_baseaddr" until the final value of "size" is known, otherwise we end up trying to map a page right after the end of memory. Fixes #112. Corresponding to flashrom svn r308 and coreboot v2 svn r3502. Signed-off-by: Segher Boessenkool <segher@kernel.crashing.org> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* ST M50FW040 TEST_OK PROBE READ ERASE WRITEPeter Stuge2008-08-081-1/+1
| | | | | | | | | Per test report from Marcel Konrad. Thanks! Corresponding to flashrom svn r307 and coreboot v2 svn r3485. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Update copyright yearStefan Reinauer2008-08-021-1/+1
| | | | | | | Corresponding to flashrom svn r306 and coreboot v2 svn r3464. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Tested another intel chipStefan Reinauer2008-08-021-1/+1
| | | | | | | Corresponding to flashrom svn r305 and coreboot v2 svn r3462. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Winbond W39V040C and MSI K8T Neo2-FPeter Stuge2008-07-215-1/+113
| | | | | | | | | | | | | | | W39V040C does standard JEDEC commands except chip erase so add a small driver. probe_w39v040c() prints the block lock pin status when a chip is found. The Neo2 board enable matches on 8237-internal IDE and onboard NIC PCI IDs. Many thanks to Daniel McLellan for testing all of this on hardware! Build tested by Uwe. Corresponding to flashrom svn r304 and coreboot v2 svn r3431. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Fix and clean up coreboot image detection heuristicCarl-Daniel Hailfinger2008-07-111-12/+20
| | | | | | | | | Additional compile fix for NetBSD. Corresponding to flashrom svn r303 and coreboot v2 svn r3420. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Trivial SPI cleanupsPeter Stuge2008-07-074-32/+15
| | | | | | | | | | | | | | | | | While writing a new SPI driver I fixed some things in the SPI code: All calls to spi_command() had unneccessary #define duplications, and in some cases the read count define could theoretically become harmful because NULL was passed for the read buffer. Avoid a crash, should someone change the #defines. I also noticed that the only caller of spi_page_program() was the it87 driver, and spi_page_program() could only call back into the it87 driver. Removed the function for easier-to-follow code and made it8716f_spi_page_program() static. The ichspi driver's static page functions are already static. Corresponding to flashrom svn r302 and coreboot v2 svn r3418. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Trivial indent fix in ichspi.cPeter Stuge2008-07-071-3/+3
| | | | | | | Corresponding to flashrom svn r301 and coreboot v2 svn r3417. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* r3415 removed symbolic constants for device IDs by accidentCarl-Daniel Hailfinger2008-07-062-3/+6
| | | | | | | | | | Flash.h is a database of known IDs, whereas flashchips.c is a database of chips for which support has been implemented. Keep it that way. Corresponding to flashrom svn r300 and coreboot v2 svn r3416. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add AMIC A29002Andreas Thienemann2008-07-062-2/+3
| | | | | | | | | | | | | | | | | | | This patch adds support to the AMIC A29002 chip in its top and bottom configuration to flashrom. Additionally, the alphabetic order of the AMIC chips was fixed. The datasheet is at <http://www.amictechnology.com/pdf/A29002.pdf>. A29002T PREW functionality was tested and works. This flash chip has asymmetric sector layout so it is important to use the mx29f002 driver, which does chip erase before writing, rather than am29f040b, which uses sector erase. Corresponding to flashrom svn r299 and coreboot v2 svn r3415. Signed-off-by: Andreas Thienemann <andreas@bawue.net> Acked-by: Peter Stuge <peter@stuge.se>
* Adding support for flashing system with Nvidia MCP67Stefan Reinauer2008-07-051-0/+1
| | | | | | | Corresponding to flashrom svn r298 and coreboot v2 svn r3414. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Add PCI IDs for EPIA-CNPeter Stuge2008-07-051-0/+2
| | | | | | | | | | Uses the 0.0 Host bridge CN700/VN800/P4M800CE/Pro and 11.0 ISA bridge devices with their 1106:aa08 subsystem id:s for autodetection. Corresponding to flashrom svn r297 and coreboot v2 svn r3413. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Minor cosmetics, e.gUwe Hermann2008-07-032-10/+7
| | | | | | | | | Make stuff fit in 80 chars/line etc. Corresponding to flashrom svn r296 and coreboot v2 svn r3412. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Mark SST49LF040B as testedCarl-Daniel Hailfinger2008-07-031-1/+1
| | | | | | | | | Thanks to Paul Seidler and Ward Vandewege for testing. Corresponding to flashrom svn r295 and coreboot v2 svn r3411. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Mark the SST SST49LF040 as OK (tested by me), all operationsUwe Hermann2008-07-031-1/+1
| | | | | | | Corresponding to flashrom svn r294 and coreboot v2 svn r3410. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Winbond W25x80 TEST_OK PROBE READ ERASE WRITEPeter Stuge2008-07-031-1/+1
| | | | | | | | | Per test report from Björn Gerhart. Thanks! Corresponding to flashrom svn r293 and coreboot v2 svn r3409. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Improve coreboot image detection heuristicCarl-Daniel Hailfinger2008-07-031-1/+13
| | | | | | | | | | It's not absolutely perfect, but the likelihood of this check to fail is 0.000000000000000000000000013 (1.3*10^-26) which is good enough for me. Corresponding to flashrom svn r292 and coreboot v2 svn r3408. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Probe_flash() cleanup for better code readabilityPeter Stuge2008-07-021-15/+15
| | | | | | | Corresponding to flashrom svn r291 and coreboot v2 svn r3407. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de>
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