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* Add missing license header to layout.cUwe Hermann2008-03-041-0/+20
| | | | | | | | | | The file was written by Stefan Reinauer for coresystems GmbH in 2005, as confirmed on IRC. Corresponding to flashrom svn r198 and coreboot v2 svn r3126. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Add board_enable for Artec Group DBE61 and DBE62Mart Raudsepp2008-02-201-0/+70
| | | | | | | | | | | Also add a comment about NULL subsystem IDs leaving the board entry out of auto-detection logic. Corresponding to flashrom svn r197 and coreboot v2 svn r3110. Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Luc Verhaegen <libv@skynet.be> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Fix compilation with custom CFLAGSClark Rawlins2008-02-141-1/+3
| | | | | | | | | | | | | | | | With this small change it is possible to build flashrom again when specifying custom CFLAGS/LDFLAGS from the make command line like. make CFLAGS="..." LDFLAGS="..." I need to do this when building flashrom in a cross compiler environment like buildroot for a foreign target. Corresponding to flashrom svn r196 and coreboot v2 svn r3102. Signed-off-by: Clark Rawlins <clark@bit63.org> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Further cleanups to enable_flash_cs5536Mart Raudsepp2008-02-111-5/+2
| | | | | | | | | | | | | | | | - Remove the "enable write to flash" message, as the caller appears to already report that. - Move the 'modprobe msr' suggestions to the first lseek64 error handling, as we get an error there already. - Rename a perror string from "read" to "read msr", as we use the latter already in this function for another read. Corresponding to flashrom svn r195 and coreboot v2 svn r3101. Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add board enable for VIA EPIA SPLuc Verhaegen2008-02-091-1/+25
| | | | | | | | Corresponding to flashrom svn r194 and coreboot v2 svn r3099. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Peter Stuge <peter@stuge.se>
* Improve error handling and make RCONF_DEFAULT_MSR address be a constantMart Raudsepp2008-02-081-26/+52
| | | | | | | | | Also, move a big code comment to the top of enable_flash_cs5536(). Corresponding to flashrom svn r193 and coreboot v2 svn r3098. Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Write enable flash chips attached to CS3 of CS5536 chipsets (AMD Geode)Mart Raudsepp2008-02-081-12/+33
| | | | | | | | | | | | | | | | This implements support for devices using AMD Geode companion chip CS5536 that have the Boot ROM on NOR flash that is directly connected to FLASH_CS3 (Boot Flash Chip Select). We need to write enable it in the NORF_CTL MSR register for flashrom to be able to write to it, including JEDEC probe commands. This patch allows us to stop using AMD gx_utils.ko for BIOS flashing on the DBE61. Corresponding to flashrom svn r192 and coreboot v2 svn r3097. Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Handle JEDEC JEP106W continuation codes in SPI RDIDCarl-Daniel Hailfinger2008-02-063-7/+40
| | | | | | | | | | | | | Some vendors like Programmable Micro Corp (PMC) need this. Both the serial and parallel flash JEDEC detection routines would benefit from a parity/sanity check of the vendor ID. Will do this later. Add support for the PMC Pm25LV family of SPI flash chips. Corresponding to flashrom svn r191 and coreboot v2 svn r3091. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Chris Lingard <chris@stockwith.co.uk>
* Make the vendor name optional in the -m flashrom parameter when there's only ↵Peter Stuge2008-01-274-35/+51
| | | | | | | | | | | | one board name that matches The full syntax still works, and is required when two vendors have boards with the same names. Corresponding to flashrom svn r190 and coreboot v2 svn r3082. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Forgot to add Spansion S25FL016A to README, trivialPeter Stuge2008-01-271-0/+1
| | | | | | | Corresponding to flashrom svn r189 and coreboot v2 svn r3080. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Correctly disable the ROM area Write Protect bit in the Geode LXMarc Jones2008-01-261-1/+1
| | | | | | | | | | Corresponding to flashrom svn r188 and coreboot v2 svn r3078. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Peter Stuge <peter@stuge.se> Tested on the pcengines alix1c and works fine. Acked-by: Ronald G. Minnich <rminnich@gmail.com>
* Add ids and chip entry for Spansion S25FL016A, tested, workingPeter Stuge2008-01-252-0/+10
| | | | | | | Corresponding to flashrom svn r187 and coreboot v2 svn r3074. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Here is just a little and simple patch to get the MX25L3205D workingHarald Gutmann2008-01-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I've tested and verified the chip myself, and it seems to work everything like supposted, since Carl-Daniel has patched flashrom to use the read funktion on verifying. "benchvice flashrom # ./flashrom -m gigabyte:m57sli -v test.4mb Calibrating delay loop... OK. No coreboot table found. Found chipset "NVIDIA MCP55", enabling flash write... OK. Found board "GIGABYTE GA-M57SLI-S4": enabling flash write... Serial flash segment 0xfffe0000-0xffffffff enabled Serial flash segment 0x000e0000-0x000fffff enabled Serial flash segment 0xffee0000-0xffefffff disabled Serial flash segment 0xfff80000-0xfffeffff enabled LPC write to serial flash enabled serial flash pin 29 OK. MX25L3205 found at physical address 0xffc00000. Flash part is MX25L3205 (4096 KB). Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... VERIFIED. benchvice flashrom # ls -l test.4mb -rw-r--r-- 1 root root 4194304 22. Jan 16:27 test.4mb Corresponding to flashrom svn r186 and coreboot v2 svn r3072. Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Flashrom did not use the read function for verifying, it used direct memory ↵Carl-Daniel Hailfinger2008-01-221-2/+6
| | | | | | | | | | | | | | | | | | | access instead That fails if the flash chip is not mapped completely. If the read function is set in struct flashchip, use it for verification as well. This fixes verification of all SPI flash chips >512 kByte behind an IT8716F flash translation chip. "MX25L8005 found at physical address 0xfff00000. Flash part is MX25L8005 (1024 KB). Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... VERIFIED." Corresponding to flashrom svn r185 and coreboot v2 svn r3070. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Harald Gutmann <harald.gutmann@gmx.net>
* Make sure we delay writing the next byte long enough in SPI byte programmingCarl-Daniel Hailfinger2008-01-221-22/+19
| | | | | | | | | Minor formatting changes. Corresponding to flashrom svn r184 and coreboot v2 svn r3069. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Harald Gutmann <harald.gutmann@gmx.net>
* Omitting the wait for SPI ready when there is no data to be read, e.gRonald Hoogenboom2008-01-211-5/+8
| | | | | | | | | | readcnt==0 saves 10 seconds with the unconditional 10us delay, reducing programming time for SST25VF016B to 40-45 secs. Corresponding to flashrom svn r183 and coreboot v2 svn r3068. Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* This patch adds version informationBernhard Walle2008-01-213-6/+23
| | | | | | | | | | | Because 'v' and 'V' are already in use, the patch uses 'R' (for release) and, of course, '--version'. Corresponding to flashrom svn r182 and coreboot v2 svn r3067. Signed-off-by: Bernhard Walle <bernhard.walle@gmx.de> Acked-by: Ulf Jordan <jordan@chalmers.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Further abstract SPI functions to allow chips bigger than 512 kB behind IT8716FsRonald Hoogenboom2008-01-193-37/+211
| | | | | | | | | | | Support SPI flash chips bigger than 512 kByte sitting behind IT8716F Super I/O performing LPC-to-SPI flash translation. Corresponding to flashrom svn r181 and coreboot v2 svn r3061. Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Minor documentation improvements/fixes in the README and manpageUwe Hermann2008-01-182-15/+24
| | | | | | | Corresponding to flashrom svn r180 and coreboot v2 svn r3059. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Rename linuxbios_* files in utils repositoryStefan Reinauer2008-01-183-2/+2
| | | | | | | Corresponding to flashrom svn r179 and coreboot v2 svn r3058. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Rename LinuxBIOS to corebootStefan Reinauer2008-01-1810-35/+35
| | | | | | | Corresponding to flashrom svn r178 and coreboot v2 svn r3054. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* This patch removes '\n' from the help output since this looks a bit strangeBernhard Walle2008-01-111-1/+1
| | | | | | | | | After the patch [...] The line length is still below 80 characters. Corresponding to flashrom svn r177 and coreboot v2 svn r3045. Signed-off-by: Bernhard Walle <bernhard.walle@gmx.de> Acked-by: Torsten Duwe <duwe@lst.de>
* Enable MX25L8005 supportHarald Gutmann2008-01-101-0/+2
| | | | | | | | | The #defines were already there. Corresponding to flashrom svn r176 and coreboot v2 svn r3042. Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add support for the SST25VF040B 4 Mbit SPI flash chipCarl-Daniel Hailfinger2008-01-071-0/+2
| | | | | | | | | Straight from the data sheet, not tested. Corresponding to flashrom svn r175 and coreboot v2 svn r3036. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Add board enable for the gigabyte ga_2761gxdk boardRonald G. Minnich2008-01-041-0/+2
| | | | | | | Corresponding to flashrom svn r174 and coreboot v2 svn r3033. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Print at least the vendor for SPI flash chips if the exact chip ID is unknownCarl-Daniel Hailfinger2008-01-043-3/+19
| | | | | | | Corresponding to flashrom svn r173 and coreboot v2 svn r3032. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com>
* Unfortunately, EN29F002T, EN29F002AT, EN29F002ANT, EN29F002NT all have ↵Carl-Daniel Hailfinger2007-12-312-4/+5
| | | | | | | | | | | | | exactly the same ID Improve model number printing. Add EN29F002(A)(N)B support while I'm at it. Corresponding to flashrom svn r172 and coreboot v2 svn r3031. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Markus Boas <bios@ryven.de>
* Add continuation ID support to jedec.cCarl-Daniel Hailfinger2007-12-314-5/+126
| | | | | | | | | | | | | | | | | | | | | | | The continuation ID code does not go further than checking for IDs of the type 0x7fXX, but does this for vendor and product ID. The current published JEDEC spec has a list where the largest vendor ID is 7 bytes long, but all leading bytes are 0x7f. The list will grow in the future, and using a 64bit variable will not be enough anymore. Besides that, it seems that the location of the ID byte after the first continuation ID byte is very vendor specific, so we may have to revisit that code some time in the future. (Suggestion for a new encoding: Use a two-byte data type for the ID, the lower byte contains the only non-0x7f byte, the upper byte contains the number of 0x7f bytes used as prefix, which is the bank number minus 1 the vendor ID appears in.) Add support for EON EN29F002AT. Corresponding to flashrom svn r171 and coreboot v2 svn r3030. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Corey Osgood <corey.osgood@gmail.com>
* Refine various vendor ID annotationsCarl-Daniel Hailfinger2007-12-313-11/+24
| | | | | | | | | | | | | | This fixes a few vendor IDs to conform with JEDEC publication 106W (JEP106W), adds some device IDs and provides information about non-conforming IDs. The EON change is left to the patch adding EON chips. This patch should have no effect on code generation. Corresponding to flashrom svn r170 and coreboot v2 svn r3029. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Corey Osgood <corey.osgood@gmail.com>
* All SPI chips mentioned in flashchips.c had their sector size listed as page ↵Carl-Daniel Hailfinger2007-12-291-10/+10
| | | | | | | | | | | | | size Fix that. Page size is uniform 256 bytes for SPI. A sector/block size field in struct flashchip would be nice, though. Corresponding to flashrom svn r169 and coreboot v2 svn r3027. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Corey Osgood <corey.osgood@gmail.com>
* Print the chip status register for all SPI chips on probe if verbose output ↵Carl-Daniel Hailfinger2007-12-291-7/+50
| | | | | | | | | | | | is specified Pretty-print the chip status register (including block lock information) for ST M25P family and Macronix MX25L family chips. Corresponding to flashrom svn r168 and coreboot v2 svn r3026. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Corey Osgood <corey.osgood@gmail.com>
* Add 25VF016B supportCarl-Daniel Hailfinger2007-12-291-0/+2
| | | | | | | | | Untested, but verified against the data sheet. Corresponding to flashrom svn r167 and coreboot v2 svn r3025. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Corey Osgood <corey.osgood@gmail.com>
* Add support for various ST M25P* chipsCarl-Daniel Hailfinger2007-12-172-0/+24
| | | | | | | | | | | | | Add support for ST M25P05-A, M25P10-A, M25P20, M25P40, M25P16, M25P32, M25P64, M25P128. ST M25P80 support is already there. Not tested, but conforming to data sheets and double checked. Corresponding to flashrom svn r166 and coreboot v2 svn r3012. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Rename SPI erase functions to include opcodeCarl-Daniel Hailfinger2007-12-173-22/+22
| | | | | | | | | | | | | | | To make it easier to add new SPI chips to flashchips.c, rename functions with multiple possible opcodes from linear numbering at the end (_1, _2) to include the opcode at the end (_60, _c7). That way, you only have to take a short look at the data sheet and choose the right function by appending the opcode listed in the data sheet. No functional changes. Corresponding to flashrom svn r165 and coreboot v2 svn r3009. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ward Vandewege <ward@gnu.org>
* Add support for ST M25P80 chipsCarl-Daniel Hailfinger2007-12-163-0/+11
| | | | | | | | | | Detection was tested. Print status register before erase to help debugging block locks. Corresponding to flashrom svn r164 and coreboot v2 svn r3008. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Corey Osgood <corey.osgood@gmail.com>
* Add support for more atmel chipsFrederico Silva2007-12-102-0/+6
| | | | | | | | | | | | | | | AT49F002 AT49F002N AT49F002T AT49F002NT Only tested the read function on AT49F002T. datasheet @ http://www.atmel.com/atmel/acrobat/doc1017.pdf Corresponding to flashrom svn r163 and coreboot v2 svn r3003. Signed-off-by: Frederico Silva <frederico.silva@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Various coding style fixes, constification, fixed typosUwe Hermann2007-12-043-140/+122
| | | | | | | | | | Also, s/0xFF80/0xFFC0/ in the Acorp 6A815EPD board-enable, as per http://www.linuxbios.org/pipermail/linuxbios/2007-December/027750.html Corresponding to flashrom svn r162 and coreboot v2 svn r2997. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add board-enable for Acorp 6A815EPDJonathan A. Kollasch2007-12-022-0/+29
| | | | | | | | Corresponding to flashrom svn r161 and coreboot v2 svn r2995. Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Flashrom support for AMD Geode CS5536Lane Brooks2007-11-131-0/+55
| | | | | | | | | | Attached is a patch that enables AMD Geode CS5536 chipset support. I have tested it successfully on a MSM800 board from digital logic. Corresponding to flashrom svn r160 and coreboot v2 svn r2967. Signed-off-by: Lane Brooks <lbrooks@mit.edu> Acked-by: Jordan Crouse <jordan.crouse@amd.com>
* Fix ATMEL 29C020 detection with flashromCarl-Daniel Hailfinger2007-11-131-2/+6
| | | | | | | | | | | | The JEDEC probe routine had a delay of 10 us after entering ID mode and this was insufficient for the 29C020. The data sheet claims we have to wait 10 ms, but tests have shown that 20 us suffice. Allow for variations in chip delays with a factor of 2 safety margin. Corresponding to flashrom svn r159 and coreboot v2 svn r2962. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se>
* Add support for Intel 440MX and Fujitsu MBM29F400TCUwe Hermann2007-10-303-0/+4
| | | | | | | | | Detection and reading works, writing is not tested. Corresponding to flashrom svn r158 and coreboot v2 svn r2903. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se>
* Add Am29LV040BPeter Lemenkov2007-10-252-0/+3
| | | | | | | | | | | | | Looking through the sources of Uniflash utility I found that this chip is no more no less than low-voltage variant of Am29F040B but with different ID. So I created a very quick patch (attached). Corresponding to flashrom svn r157 and coreboot v2 svn r2897. Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Acked-by: Peter Stuge <peter@stuge.se>
* Add more Vendor IDs and ensure correct sorting in flash.hPeter Lemenkov2007-10-221-27/+45
| | | | | | | Corresponding to flashrom svn r156 and coreboot v2 svn r2884. Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Introduce block and sector erase routines, but do not use them yetCarl-Daniel Hailfinger2007-10-223-15/+86
| | | | | | | Corresponding to flashrom svn r155 and coreboot v2 svn r2881. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Remove hardcoded wait from SPI write/erase routines and check the chip ↵Carl-Daniel Hailfinger2007-10-181-18/+2
| | | | | | | | | | | | status register instead This has been tested by Harald Gutmann <harald.gutmann@gmx.net> with a MX25L4005 chip. Corresponding to flashrom svn r154 and coreboot v2 svn r2876. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Documentation fixes and updatesUwe Hermann2007-10-182-28/+37
| | | | | | | Corresponding to flashrom svn r153 and coreboot v2 svn r2875. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add generic SPI flash erase and write supportCarl-Daniel Hailfinger2007-10-183-6/+129
| | | | | | | | | | | | | The first chip the code was tested and verified with is the Macronix MX25L4005, but other chips should work as well. Timeouts are still hardcoded to data sheet maxima, but the status register checking code is already there. Thanks to Harald Gutmann for the initial code on which this is loosely based. Corresponding to flashrom svn r152 and coreboot v2 svn r2874. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Some cosmetic cleanups in the flashrom code and outputUwe Hermann2007-10-1720-49/+48
| | | | | | | Corresponding to flashrom svn r151 and coreboot v2 svn r2873. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Fix wrong values/typos in chipset_enable.cCarl-Daniel Hailfinger2007-10-171-2/+2
| | | | | | | | | | This has been confirmed by Ed Swierk in http://www.mail-archive.com/linuxbios@linuxbios.org/msg09788.html . Corresponding to flashrom svn r150 and coreboot v2 svn r2868. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Multiple flashrom fixesUwe Hermann2007-10-162-2/+4
| | | | | | | | | | | | | | - Install binary in /usr/sbin (not /usr/bin), as it's a root-only tool. - Rename manpage from flashrom.1 to flashrom.8, as section 8 contains "System administration commands (usually only for root)". - Actually install the manpage upon 'make install'. Corresponding to flashrom svn r149 and coreboot v2 svn r2866. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de>
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