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* linux_mtd: Mark Opaque chip as tested for WPAnastasia Klimchuk2022-11-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Since linux_mtd supports write-protect, its probe function needs to mark Opaque chip as tested for WP. Programmers which are opaque masters are responsible for populating flashchip#tested struct in probe function. Without the patch, any operation running via linux_mtd displays a message "This flash part has status UNTESTED for operations: WP". With the patch, the message is not displayed anymore. BUG=b:258755442 BRANCH=none TEST=flashrom -p host on ARM dut Found Programmer flash chip "Opaque flash chip" (8192 kB, Programmer-specific) on host. No operations were specified. Change-Id: Icc0521c28555a93f26ce66bdbeaa68590f10c358 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
* cli_classic.c: Be consistent with pointer typesAngel Pons2022-11-211-2/+2
| | | | | | | | | | | | | | | With `i586-pc-msdosdjgpp-gcc (GCC) 12.2.0`, `uint32_t` is defined as `long unsigned int`, which is not the same as `unsigned int`. As the `flashrom_layout_get_region_range()` function is part of libflashrom API, adjust `cli_classic.c` instead to avoid type mismatches. Change-Id: Ie8f5bc0d9296f7c6b8f8a351b53052f5fe86b09d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69451 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Evan Benn <evanbenn@google.com> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: enable WP for 7 entries of MX chipsSergii Dmytruk2022-11-191-4/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These weren't split: * MX25L3206E/MX25L3208E Tested: https://github.com/Dasharo/flashrom/pull/8 * MX25L6405 * MX25L6405D * MX25L6406E/MX25L6408E Tested: https://github.com/Dasharo/flashrom/pull/8 MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E/MX25L6473F was split into: * MX25L6436E/MX25L6445E/MX25L6465E - security register - WPS - tested: https://github.com/Dasharo/flashrom/pull/8 * MX25L6473E - security register - OTP TB bit in CONFIG/STATUS2 (0x15 opcode) - WPS * MX25L6473F - NO security register - OTP TB bit in CONFIG/STATUS2 (0x15 opcode) - NO WPS Change-Id: Ib3db9d39ffacd3e9e44de92c6cfb6c3ecc8615bd Tested-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips.c: enable WP for MT25QL512, N25Q0{32,64}..{1,3}ESergii Dmytruk2022-11-191-0/+51
| | | | | | | | Change-Id: Ib0f3cb9516cea7bb678842a358a82099221e1ed9 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66215 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: enable WP for W25Q32.V, W25Q32.W and W25Q32JW...MSergii Dmytruk2022-11-191-6/+248
| | | | | | | | | | | | Split chips: * W25Q32.V -> W25Q32BV/W25Q32CV/W25Q32DV, W25Q32FV and W25Q32JV * W25Q32.W -> W25Q32BW/W25Q32CW/W25Q32DW, W25Q32FW and W25Q32JW...Q Change-Id: Id259c27dfa6c681bbadc73b3bd7559ad6a5865f4 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips.c: enable WP for EN25QH32 and EN25QH64Sergii Dmytruk2022-11-191-0/+96
| | | | | | | | | | | | | | | Split chips: * EN25QH32 -> EN25QH32 and EN25QH32B * EN25QH64 -> EN25QH64 and EN25QH64A Unlike older revisions both newly added EN25QH32B and EN25QH64A support half block (32KiB) erase operation via 0x52 opcode. Change-Id: I759f0119346235ce0bddc78cde9c461495990c25 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* writeprotect_ranges.c: add more range functionsSergii Dmytruk2022-11-194-12/+73
| | | | | | | | | | | | Not all chips follow the same pattern. There are differences in how CMP bit is treated or in block size used. Change-Id: Ied7b27be2ee2426af8f473432e2b01a290de2365 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66212 Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25_statusreg: support reading/writing configuration registerSergii Dmytruk2022-11-193-0/+33
| | | | | | | | | | | | | | One more variation of registers. This one is read via a separate RDCR command, but written as if it's SR2 using WRSR_EXT2. Change-Id: I45f9afcc31f1928ef6263a749596380082963de4 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66211 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25_statusreg.c: support reading security registerSergii Dmytruk2022-11-193-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | Not to be confused with "secure registers" of OTP. Security register is a dedicated status register for security-related bits. You don't write its value directly, issuing special write commands with no data set separate OTP bits to 1 automatically (WRSCUR, WPSEL commands). No WREN is necessary, but at least some datasheets indicate BUSY state after those write commands. Unlike cases where OTP bit is part of SR and can only be written while in OTP mode, security register can only be written outside of the mode. The register is found in at least these chips by Macronix: * MX25L6436E * MX25L6445E * MX25L6465E * MX25L6473E Change-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59709 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* stlinkv3_spi: work around false-positive compiler errorAlexander Goncharov2022-11-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | | `stlinkv3_handle` is declared without an initial value. The variable is initialized in a branch which can only be accessed if `devs_stlinkv3_spi[0].vendor_id != 0`. Otherwise, the variable contains a garbage value. We can consider this case as a false positive because `devs_stlinkv3_spi` holds as a minimum one device entry (otherwise we wouldn't need a driver). This issue was found by setting compiler flag `-Og`, which optimizes debugging experience, and running scan-build. So, we have to work around it to allow the compiler to use the flag and remove the warning from the scan-build list. Change-Id: Ibaf25f67186724d9045ade849026782c3eac4952 Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* writeprotect.c: refuse to work with chip if OTP WPS == 1Sergii Dmytruk2022-11-183-3/+23
| | | | | | | | | | | | | Perform the check right in read_wp_bits() as it's used by various WP operations and also because its results won't make sense if WPS bit is on and can't be changed. Change-Id: I143186066a1d3af89809b7135886cb8b0d038085 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* writeprotect.c: skip unnecessary writesSergii Dmytruk2022-11-181-17/+28
| | | | | | | | | | | | * Don't write register because of RO and OTP bits. * Skip the write of RW bits if register state wouldn't change by it. Change-Id: I81d2d3fc0a103ee00ced78838d77fe33a9d3056a Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* flashrom_tester: Only print color when stdout isattyEvan Benn2022-11-174-25/+57
| | | | | | | | | | | | | | | | | Add the atty crate as a dependency. Print log and report in color only when isatty is true. BUG=b:246250254 BRANCH=None TEST=ssh dut flashrom_tester # no color TEST=ssh -t dut flashrom_tester # color Change-Id: Ia3cc527fb98e53eda6773622340cf10764df2cba Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashrom_tester: Change timestamp to UTC microsecondEvan Benn2022-11-171-2/+2
| | | | | | | | | | | | | | Match the timestamp with dmesg and other logs for ease of comparing. BUG=b:246250254 BRANCH=None TEST=flashrom_tester --libflashrom host Change-Id: I05182f52c0e9392a4fa2b388fdc30633e5d6e5ef Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* tests: ensure chip erase operation is executedNikolai Artemiev2022-11-132-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | The `full_chip_erase_with_wp_dummyflasher_test_success` test case checks that erasing a write-protected region of a dummyflasher chip fails. However erase optimization may cause the erase operation to be skipped if the flash contents are already erased, so the erase operation appears to succeed and the test case fails. Writing a non-erased value to the chip ensures that an erase operation will be executed and write protection will be properly tested. BUG=b:237620197 BRANCH=none TEST=ninja test Change-Id: Ia00444dcd2ad96c64832a13201efbd064cd7302d Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* programmer: Drop dead fallback_map() boilerplateEdward O'Callaghan2022-11-124-25/+8
| | | | | | | | | | | | | | The fallback_{un}map() boilerplate code doesn't do anything, merely distracts away from otherwise linear control flow. Just drop it as anything in the future that could need such a thing is free to implement it when required. Change-Id: Ibb7760f807fae040416cef2797a7dbf6572f7df9 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68963 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* meson: Move programmer test sources into programmer definitionFelix Singer2022-11-112-9/+14
| | | | | | | | | | | | | | | | | Move the definition of the programmer test source files into the dictionary defining the programmers itself. This way there is a better overview about which of the available programmers have tests and which don't. Also, to keep the tests working, iterate over all programmers and add their test source files to the list of sources that should be built. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I307faaf8a9f7ae3c54bd96e7d871a3abb8aadea3 Reviewed-on: https://review.coreboot.org/c/flashrom/+/68162 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Convert flashchip erase_block func ptr to enumerateEdward O'Callaghan2022-11-117-47/+108
| | | | | | | | | | | | | | This forges the way for flashchips.c to be pure declarative data and lookup functions for dispatch to be pure. This means that the flashchips data could be extracted out to be agnostic data of the flashrom code and algorithms. Change-Id: I02ae7e4c67c5bf34ec2fd7ffe4af8a2aba6fd5e5 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69133 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Convert flashchips db to use indirection for erase_blockEdward O'Callaghan2022-11-119-1971/+2007
| | | | | | | | | | | | | | This paves the way to allow for the conversion of flashchip erase_block func ptr to enumerate values. This change should be a NOP. TEST=`diff -u <(objdump -D flashchips.o_bk) <(objdump -D flashchips.o)`. Change-Id: I122295ec9add0fe0efd27273c9725e5d64f6dbe2 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69131 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add write protect bits to W25Q64JW...MEvan Benn2022-11-101-1/+12
| | | | | | | | | | | | | | | https://www.winbond.com/hq/support/documentation/levelOne.jsp?__locale=en&DocNo=DA00-W25Q64JW BUG=b:245996788 BRANCH=None TEST=None Change-Id: Idf2289b7c90724ececc122d2a05c7cae3af2cf62 Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* tree/: Rename ERROR_NONFATAL to ERROR_FLASHROM_NONFATALEdward O'Callaghan2022-11-093-13/+13
| | | | | | | | | | Change-Id: I5c30fec0cebab2b7d10e2789761889abc3a14dd3 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68777 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Rename ERROR_FATAL to ERROR_FLASHROM_FATALEdward O'Callaghan2022-11-099-43/+43
| | | | | | | | Change-Id: I51ee789f9a1443bfff1e3c85c9b40b5023db6062 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* bitbang_spi.c: Fix unchecked heap allocationEdward O'Callaghan2022-11-091-0/+3
| | | | | | | | | Change-Id: Ib64b1fe67fa1874875453ab9e1700e468c579e7c Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* flashrom_tester: Use path types for things that are pathsEvan Benn2022-11-096-69/+79
| | | | | | | | | | | | | | | | Use Path and PathBuf for things that are paths. BUG=b:243460685 BRANCH=None TEST=/usr/bin/flashrom_tester --flashrom_binary /usr/sbin/flashrom host TEST=/usr/bin/flashrom_tester --libflashrom host Change-Id: I69531bec5436a60430eae975eeab02c8835962bf Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashrom_tester: Move layout_file to TestEnvEvan Benn2022-11-092-24/+37
| | | | | | | | | | | | | | | | | | layout_file is part of the test environment, move it from a global to a member of the TestEnv struct. This allows layout to be part of the tempdir in a subsequent patch. BUG=b:243460685 BRANCH=None TEST=/usr/bin/flashrom_tester --flashrom_binary /usr/sbin/flashrom host TEST=/usr/bin/flashrom_tester --libflashrom host Change-Id: Ia7e8efeb4fbac0a46627f079956d671aed43f1c7 Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69063 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tests: Add prefix to io_mock functions not to clash with macrosAnastasia Klimchuk2022-11-088-43/+43
| | | | | | | | | | | | | | | | | | | | Flashrom I/O mock functions need to be renamed so that they do not have name clash with standard I/O, because the latter are allowed to be macros. Adding a prefix to flashrom mock functions avoids them being accidentally expanded. Standard I/O functions are expanded and flashrom mocks stay as they are. BUG=b:237606255 TEST=ninja test 1) gcc 12.2.0 on Debian 2) clang 15.0 on Chromium OS Ticket: https://ticket.coreboot.org/issues/411 Change-Id: I7998a8fb1b9e65621e12adbfab5460a245d5606b Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tests: Undefine _FORTIFY_SOURCE for unit tests to avoid _chk variantsAnastasia Klimchuk2022-11-072-18/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The option _FORTIFY_SOURCE, when enabled, can result in some functions being expanded into _chk variants. For example, `fprintf` can get expanded into `__fprintf_chk`. This makes sense for building a real binary, but is not needed for unit tests. In unit test environment all those functions are wrapped. In the example above, both `fprintf` and `__fprintf_chk` needed to be mocked. Disabling _FORTIFY_SOURCE avoids expanding functions into _chk variants, without any loss of testing coverage because that would be wrapped/mocked anyway. This patch also removes two existing _chk wraps because they are not needed anymore. BUG=b:237606255 TEST=ninja test on 1) gcc 12.2.0 on Debian 2) clang 15.0 on Chromium OS Ticket: https://ticket.coreboot.org/issues/411 Change-Id: I70cb1cd90d1f377ff4606acad3c1b514120ae4f7 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68432 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashrom.c: Make 'chip_to_probe' a param to probe_flash()Edward O'Callaghan2022-11-066-18/+27
| | | | | | | | | | | | | | | | | Apart from the very bespoke case of 'probe_w29ee011()' the override 'chip_to_probe' name is a nature parameter to 'probe_flash()'. However we can deal with w29ee011 by providing a probe specific validation function to check if the chip can indeed be overriden. TEST=`./flashrom -p internal --flash-name`. Change-Id: Ifcdace07ea2135d83dea92cfa5c6bec8d7ddf05d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* Makefile: Don't install git hooks automaticallyFelix Singer2022-11-041-3/+3
| | | | | | | | | | | | | | | | | | These specific git hooks are only needed when someone wants to push a patch to upstream and so it's not needed to run it in every make call. Beside that, we also don't know the environment in which this is executed and it might not be wanted. Thus, add a new make target `gitconfig` and move the install command to it. It can be used by running `make gitconfig`. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: Ib83568c7ff149a8ec34ad7e92720c36a89def7bd Reviewed-on: https://review.coreboot.org/c/flashrom/+/68647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* ichspi.c: heap allocate hwseq_data to remove globalEdward O'Callaghan2022-11-031-6/+18
| | | | | | | | | | | | Align hwseq path in ichspi with the rest of the flashrom tree by making hwseq_data a heap allocation within the life-time of the driver managed by the driver registration API. Change-Id: Ib362c5ab2d3e8afee2c3c7d3135cc4414d6bd6c3 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* ichspi.c: derive hsfc_fcycle from ctx in ich_start_hwseq_xfer()Edward O'Callaghan2022-11-031-1/+2
| | | | | | | | | | | | | Allow helpers to derive driver specific data from the driver specific context instead of being a closure over a static global variable. Change-Id: Ib0ccf4b32fd1e2be2ecc3a4a4c6e397c8e901a0a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Subrata Banik <subratabanik@google.com>
* ichspi.c: plumb flashctx through hwseq xfer helperEdward O'Callaghan2022-11-031-8/+9
| | | | | | | | | | | | Change is a NOP to prepare ichspi to remove hwseq_data being a global symbol in CB:68774. This allows for the helper functions to derive their data from the driver data context. Change-Id: I67b5aa6350930d912e5036473ac3e792debac0bd Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tests/meson.build: Rename list of source files to `test_srcs`Felix Singer2022-11-011-3/+3
| | | | | | | | | | | | Rename the list of source files to `test_srcs` so that there is less confusion with the variable `srcs` from the top-level meson.build file containing the flashrom source files. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: Ica0fc3923070bff63323204bd58edb5276dc9493 Reviewed-on: https://review.coreboot.org/c/flashrom/+/68228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* tree/: Convert flashchip read func ptr to enumerateEdward O'Callaghan2022-11-017-607/+654
| | | | | | | | | | | | | | | | This forges the way for flashchips.c to be pure declarative data and lookup functions for dispatch to be pure. This means that the flashchips data could be extracted out to be agnostic data of the flashrom code and algorithms. TEST='R|W|E && --flash-name' on ARM, AMD & Intel DUT's. Change-Id: I612d46fefedf2b69e7e2064aa857fa0756efb4e7 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66788 Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Convert flashchip write func ptr to enumerateEdward O'Callaghan2022-11-017-599/+656
| | | | | | | | | | | | | | | | This forges the way for flashchips.c to be pure declarative data and lookup functions for dispatch to be pure. This means that the flashchips data could be extracted out to be agnostic data of the flashrom code and algorithms. TEST='R|W|E && --flash-name' on ARM, AMD & Intel DUT's. Change-Id: I80149de169464b204fb09f1424a86fc645b740fd Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tree/: Convert flashchip probe func ptr to enumerateEdward O'Callaghan2022-11-014-596/+650
| | | | | | | | | | | | | | | | This forges the way for flashchips.c to be pure declarative data and lookup functions for dispatch to be pure. This means that the flashchips data could be extracted out to be agnostic data of the flashrom code and algorithms. TEST='R|W|E && --flash-name' on ARM, AMD & Intel DUT's. Change-Id: I00aaab9c83f305cd47e78c36d9c2867f2b73c396 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* writeprotect: Add some debug logging if wp_verify failsEvan Benn2022-10-311-3/+8
| | | | | | | | | | Change-Id: I5fcaf767570418f90ae44826a1135d9b49653033 Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67720 Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* chipset_enable.c: Mark Intel C246 as DEPAngel Pons2022-10-311-1/+1
| | | | | | | | | | | | Tested reading, writing and erasing the flash chip of a Prodrive Hermes mainboard with an Intel C246 PCH. However, since ME-enabled chipsets are marked as DEP instead of OK, this one shall also be. Change-Id: I07d6c4a60e468c61eba836db91e1335f4a762048 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* nicintel_eeprom.c: Fix typoFelix Singer2022-10-311-4/+4
| | | | | | | | | | | `done_i20_write` is meant to be `done_i210_write`. Fix that. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: Idc0a0c475e891fc8538a7a81093520e01e1b25bf Reviewed-on: https://review.coreboot.org/c/flashrom/+/68582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Alexander Goncharov <chat@joursoir.net>
* MAINTAINERS: Add Felix Singer for test_build.shFelix Singer2022-10-311-0/+5
| | | | | | | | | Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I36267e6c080b14e90e820d3e26abaefe642f9c65 Reviewed-on: https://review.coreboot.org/c/flashrom/+/67269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashrom.c: Move count_max_decode_exceeding() to cliEdward O'Callaghan2022-10-313-44/+43
| | | | | | | | | | | | The count_max_decode_exceeding() function is only ever called within the cli_classic logic so move it there and make it static. This further cleans up the flashrom.c symbol namespace. Change-Id: If050eab7db8560676c03d5005a2b391313a0d642 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68438 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Convert flashchip decode range func ptr to enumNikolai Artemiev2022-10-284-28/+51
| | | | | | | | | | | | | | | | | | | | Replace the `decode_range` function pointer in `struct flashchip` to an enum value. The enum value can be used to find the corresponding function pointer by passing it to `lookup_decode_range_func_ptr()`. Removing function pointers like `decode_range` makes it possible to represent chip data in a declarative format that does not have to be stored as C source code. BUG=b:242479049 BRANCH=none TEST=ninja && ninja test Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Change-Id: If6d08d414d3d1ddadc95ca1d407fc87c23ab543d Reviewed-on: https://review.coreboot.org/c/flashrom/+/67195 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: mark WP of 9 entries as testedSergii Dmytruk2022-10-231-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is based on information from: * commit a850fd0aa8054a1125a9231fa3317428f15900f4 - GD25LQ128C/GD25LQ128D/GD25LQ128E - GD25LQ64(B) - GD25Q127C/GD25Q128C - GD25Q256D/GD25Q256E - GD25Q64(B) * commit a8204dd34d90ac9ab2783e1dd486ec781d4c0dba - GD25Q32(B) * commit 7b4c4f36113c4b7ed5c985d4cf51733639e69bf8 - W25Q64BV/W25Q64CV/W25Q64FV * https://github.com/Dasharo/dasharo-issues/issues/67 - W25Q128.V..M * https://github.com/Dasharo/flashrom/pull/8 - W25Q64.W Change-Id: I090188bad568885f78778e7fc7d8dbe20fb2445f Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: Nikolai Artemiev <nartemiev@google.com> Tested-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: Kamil Pokornicki <kamil.pokornicki@3mdeb.com> Tested-by: Przemyslaw Banasiak <przemyslaw.banasiak@3mdeb.com> Tested-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68180 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flash.h: extend `struct tested` with .wp fieldSergii Dmytruk2022-10-233-12/+23
| | | | | | | | | | | | Using "B" letter for "block protection" in TEST_* macros. Ticket: https://ticket.coreboot.org/issues/377 Change-Id: I791400889159bc6f305fb05f3e2dd9a90dbe18a4 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68179 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* rayer_spi.c: Get rid of temporary `prog_type` stringAngel Pons2022-10-221-14/+8
| | | | | | | | | | | | | Make the `get_params()` function provide a pointer to `struct rayer_programmer` directly, instead of having a `prog_type` string passed around three functions. Change-Id: I83e34382ee9814f224025e21e5099fdab73cee8c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68239 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* rayer_spi.c: Roll up programmer type search logic into funcEdward O'Callaghan2022-10-221-24/+33
| | | | | | | | | | | | Roll up the programmer type table search and match logic into it's own function and lexically scope the 'rayer_spi_types' table into the function while we are here. Change-Id: Id226ea61132ecc30fd8696e1d8ea50373e752cac Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* rayer_spi.c: Drop lpt_outbyte intermediate varEdward O'Callaghan2022-10-221-5/+2
| | | | | | | | | | | | | The intermediate variable in this case serves no extra assistance in readability or additional control flow branching. Just assign the result directly into the driver state tracker. Change-Id: Idedabb7b1c401d666b3b7e621e75704c7e765fd1 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* rayer_spi.c: Move param parse logic into own funcEdward O'Callaghan2022-10-221-21/+36
| | | | | | | | | | | Deconvolve programmer parameter parse logic out of main 'rayer_spi_init()' entry-point function control flow. Change-Id: I287aa2e5d94e872553d08c0750f8dc6d60b9caff Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68230 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* raiden_debug_spi: Remove fixme with explanationLiam Flaherty2022-10-211-1/+5
| | | | | | | | | | | | | | | | | | The raiden_debug_spi programmer will query the connected USB devices and match against criteria other than the pid rather than iterate through the vid:pid table. The fixme has been updated to explain why the dev_entry table is empty. TICKET: https://ticket.coreboot.org/issues/394 BUG=b:253320285 TEST=build Change-Id: I43e364c02f42dd499d3c9ca3e0a03ead673da3e6 Signed-off-by: Liam Flaherty <liamflaherty@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tree: provide flashrom context into programmer_delay()Alexander Goncharov2022-10-1726-96/+97
| | | | | | | | | | | | | | | | | Modify the `programmer_delay` function signature to allow passing the flashrom context. Programmers that depend on internal delay should provide NULL as a context. The use of this function parameter will be introduced in CB:67393. TOPIC=programmer_handle_global TEST=builds Change-Id: Ibb0bce26ce2052853ee52158d7ba742967a9e229 Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 22:55:20 +0000