| Commit message (Collapse) | Author | Age | Files | Lines |
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Add Winbond W25Q512NW-IM chip ID and specs to flashrom.
BUG=b:200173901
BRANCH=none
TEST=flash W25Q512NW-IM using CCD.
Original-Change-Id: I9debeda01d77444a5ebe9808ff80a337f320ef65
Original-Signed-off-by: Atul Dhudase <adhudase@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/3171890
Original-Reviewed-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Shelley Chen <shchen@chromium.org>
Original-Commit-Queue: Shelley Chen <shchen@chromium.org>
(cherry picked from commit facb282e8939b8e4ad15d2478ed9ef86d98aed61)
Note: this commit was cherry-picked from the cros tree but
includes corrections to errors in the original commit's 4BA
feature flags that were spotted by Angel Pons
Change-Id: I9debeda01d77444a5ebe9808ff80a337f320ef65
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Currently, WARNERROR is hardcoded to 'yes' which is what we want most of
the time, but there are cases (such as when building with -fanalyzer)
that we don't want it enabled, so we see the entire output of the build,
and it doesn't halt at the first error. Removing the WARNERROR line
from the script allows the variable to be overridden from an environment
variable.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iea931e57f2a6992762566dc3dbaae8bb8df5b226
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62745
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Meson looks up if the file xyz.c exists when calling file('xyz.c').
Furthermore it keeps track of the directory of the file. This is handy
when using multiple directories.
Change-Id: I346b5468b4203f1521ec73a90f93ff3b13ebf43c
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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The JW is the only known variant. A W25Q256FW may have existed with
less 4BA instructions supported, but it never showed up and no data-
sheet is available.
Used the datasheet from here:
https://www.winbond.com/resource-files/w25q256jw%20spi%20revb%2012082017.pdf
Change-Id: I9a3995c66ad7b74823e17984bf1ffac50b5663e0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Ticket: https://ticket.coreboot.org/issues/362
Reviewed-on: https://review.coreboot.org/c/flashrom/+/44810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Add bit that was missed in `commit a850fd0a`
BUG=b:182223106
BRANCH=none
TEST=builds
Change-Id: I1cb400f6b8542a9054875b8f2557db1cc06292e2
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64607
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Projects using libflashrom like fwupd expect the user to wait for the
operation to complete. To avoid the user thinking the process has
"hung" or "got stuck" report back the progress complete of the erase,
write and read operations.
Add a new --progress flag to the CLI to report progress of operations.
Include a test for the dummy spi25 device.
TEST=./test_build.sh; ./flashrom -p lspcon_i2c_spi:bus=7 -r /dev/null --progress
Change-Id: I7197572bb7f19e3bdb2bde855d70a0f50fd3854c
Signed-off-by: Richard Hughes <richard@hughsie.com>
Signed-off-by: Daniel Campello <campello@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/49643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
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Set `flash->chip_restore_fn_count` to zero before calling the chip's
unlock funciton in `prepare_flash_access()`.
Previously `flash->chip_restore_fn_count` was uninitialized before
calling `chip->unlock()` and subsequently reset after the dispatch by
initializing it. This caused the restore handler that is registered
within `spi_disable_blockprotect_generic()` to be lost.
BUG=b:228945411
BRANCH=none
TEST=enable wp; flashrom -w; check wp still enabled.
Change-Id: I4c7df424bd2ae2b5fb2a2ab6b47a3c9ff3233acf
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add ADL PCH-S device IDs to enable flashrom on Alder Lake-S platforms.
TEST=Dump BIOS on MSI Z690 PRO DDR4 WIFI
Change-Id: Ib2a8c057994874a41ed400b176f156048dae43c0
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
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libjaylink is packaged since NixOS 21.11 and it is out for many months
now. Thus, include the package libjaylink and remove comments.
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: I56e750831143a4e34be95ec111a37bb476abfe85
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64352
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If parameter --wp-region is used and wp_region is allocated,
free the last one at the exit of the application.
Found-by: scan-build, clang v13.0.1
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Change-Id: I8520e302e9d63ed1215c5d9beb90a93fb52a91fe
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
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These were part of the original wp implementation, now dead
code left over.
Change-Id: I43b25175c6ff833b822a93c4e752a28cf97d64b8
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The need_erase() helper is only used within flashrom.c
Change-Id: Ic0946bb109fca2fc18e15eefa11cccea284ded0b
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Aspire towards a goal of making cli_classic more of just
a user of libflashrom than having quasi-parallel paths in
flashrom.c
This converts remaining read_flash_to_file() usage to the
do_read() provider wrapper around libflashrom.
BUG=b:208132085
TEST=`
sudo ./flashrom -p ft2232_spi:type=232H,divisor=1000 -f -r out -c W25X05
Flashrom output:
No EEPROM/flash device found.
Force read (-f -r -c) requested, pretending the chip is there:
Assuming Winbond flash chip "W25X05" (64 kB, SPI) on ft2232_spi.
Please note that forced reads most likely contain garbage.
Block protection could not be disabled!
Reading flash... done.
Data read:
xxd out-1khz
00000000: 0000 07ff ffff e000 0000 7fff fffe 0000 ................
00000010: 0007 ffff ffe0 0000 007f ffff fe00 0000 ................
00000020: 07ff ffff e000 0000 7fff fffe 0000 0007 ................
00000030: ffff ffe0 0000 007f ffff fe00 0000 0fff ................
xxd out-100khz
00000000: b6db 6db6 db6d b6db 6db6 db6d b6db 6db6 ..m..m..m..m..m.
00000010: db6d b6db 6db6 db6d b6db 6db6 db6d b6db .m..m..m..m..m..
00000020: 6db6 db6d b6db 6db6 db24 9249 2492 4924 m..m..m..$.I$.I$
00000030: 9249 2492 4924 9249 2492 4924 9249 2492 .I$.I$.I$.I$.I$.
`
Change-Id: I4b690b688acf9d5deb46e8642a252a2132ea8c73
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Tested-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
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This fixes -Werror=unused-function when not all programmer tests are
build.
`run_basic_lifecycle` and `run_probe_lifecycle` need to have a prototype
to not throw a -Werror=unused-function if no programmer needs them.
Change-Id: I02880e73996b30df618738e86b8a52126fbe5b3b
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
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TEST: meson build && ninja -C build
Read chip successfully with ch341a_spi programmer
Change-Id: Ic522610f59e00299ebfa1bd29482ff92120ec52b
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64030
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I9538b0aee31b294844d4f4ca0396334a81dfb498
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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The install functions of meson can take a relative path and join the
prefix automatically.
Change-Id: I9cb9faf4bdbcfd66098478cc3a260eb3b664a2e6
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
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During development it can be useful to disable unit testing. By default
tests are built if cmocka is found. To force enable tests run `meson
build -Dtests=enable`. To disable tests run `meson build
-Dtests=disabled`.
Change-Id: I384c904c577b265dfe36bf46bf07c641bc29de9b
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Move build instructions for files inside the `platform/` directory to
`platform/meson.build`. This contains instructions to build
`memaccess.c`, the right endian implementation and selecting the right
legacy command line option for the endian.
The `platform/` directory should contain code that abstracts the
underlying platform but is not involved in flashrom logic.
Change-Id: I88044a3f903f316138483dd872a6d95f8686ae69
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
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Change-Id: Ice1437cb294729b6af0e24f0a02692459b7a1412
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Change-Id: I6afb65fabf858449f2706bf250588225a94c1871
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I921be8a8a99b93d23c1dbd4ea54672ba9998558d
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
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An issue was discovered in the sys-info crate before 0.8.0 for Rust.
sys_info::disk_info calls can trigger a double free. To prevent any
potential problems, update this crate to version 0.9 (as of writing,
sys-info version 0.9.1 is the latest).
Refer to CVE-2020-36434 for more details about the sys-info crate bug.
TEST=Run `cargo build` in `util/flashrom_tester`, it still works fine.
Change-Id: I3b6b21e830ff3107860f7bcbfe2d58b29efe0c12
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63975
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tests both WP implementation and its emulation in dummy programmer.
Change-Id: I49af7f6d173eb4c56c22d80b01a473b8c499c0f8
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Start taking bits related to write protection into account.
Also add "hwwp" parameter for dummy programmer that sets state of WP
pin (not inverted value).
TEST=use command-line interface to run WP-related commands
dummyflasher doesn't store state of the chip between runs and flashrom
allows running only one command, so testing WP in this way is limited.
However, WP options can be combined with other operations and are
executed prior to them, so certain scenarios can be checked.
List possible ranges:
flashrom -p dummy:emulate=W25Q128FV,hwwp=yes --wp-list
Set a particular range and check status is correct:
flashrom -p dummy:emulate=W25Q128FV,hwwp=yes \
--wp-enable \
--wp-range=0x00100000,0x00f00000 \
--wp-status
Enable write protection and try erasing/writing (erasing here):
# this fails
flashrom -p dummy:emulate=W25Q128FV,hwwp=yes \
--wp-range=0,0x00c00000 \
--wp-enable \
--erase
Write protecting empty range has no effect:
# this succeeds
flashrom -p dummy:emulate=W25Q128FV,hwwp=yes \
--wp-range=0,0 \
--wp-enable \
--erase
Disabling WP is possible if hwwp is off:
# this fails
flashrom -p dummy:emulate=W25Q128FV,spi_status=0x80,hwwp=yes \
--wp-disable
# this succeeds
flashrom -p dummy:emulate=W25Q128FV,spi_status=0x80,hwwp=no \
--wp-disable
Change-Id: I9fd1417f941186391bd213bd355530143c8f04a0
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Enable emulation of SR2 and SR3 for W25Q128FV and provide logic for
updating them (masks of read-only bits that can't be set from outside).
TEST=check how input value affects status registers of emulated chip
flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x12 |
grep -A3 'Initial status registers'
flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x1234 |
grep -A3 'Initial status registers'
flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x123456 |
grep -A3 'Initial status registers'
Change-Id: I79f9b4a0b604663d3288ad70dcbe3ea4075dede5
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Change-Id: I9192461281f9e760644a241148f4c5100f76da98
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64246
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Prepare everything for emulating SR2 and SR3 for chips that have it.
This is needed for accessing SRP1 and WPS bits which are involved in
write protection. The emulated register doesn't affect anything yet
and will be tested by write-protection tests.
TEST=check how input value affects status registers of emulated chip
flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x12 |
grep 'Initial status register'
flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x1234 |
grep 'Initial status register'
flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x123456 |
grep 'Initial status register'
Mind that at this point there are no chips that emulate more than one
status register.
Change-Id: I177ae3f068f03380f5b3941d9996a07205672e59
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
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In function sp_stream_buffer_op, the variable parms might be NULL when
passed to memcpy. Although, since parmlen is also 0 at that time I
don't think it would make much difference. Still, add a NULL check
before calling memcpy to be safe.
Change-Id: I850123237e328f9548ba7f77a01888be2cbc9e7b
Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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These inline functions and macros are only used in
platform/endian_(big|little).c and do not need to be compiled into every
object which includes `platform.h`.
Change-Id: Ib2326e6a4eb5e000a0eace857d040372e2e9e561
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The doxygen documentation was in the libflashrom.c file. Move the
documentation to the libflashrom.h file. This allows foreign function
interface binding generators (eg rust bindgen) that operate on the .h
file to generate documentation for the target language. Some doxygen
errors were also corrected, mostly undocumented or wrongly labeled
parameters.
To test, I have diffed and inspected the doxygen documentation before
and after the change. All functions are documented the same, and the
structs and enums are now also included in the docs.
Change-Id: I856b74d5bfea13722539be15496755a95e701eea
Signed-off-by: Evan Benn <evanbenn@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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BUG=b:224358254
TEST=`man ./flashrom.8.tmpl`.
Change-Id: I186920006bdfcc7a9f89542f84b452dfc72b18e4
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
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Change-Id: I3d8e3dbd5eeb057d7c959a82678cca2345fc69d9
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
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Just a trivial patch to fix a few errors found by codespell.
Here's the command I used:
codespell -S subprojects,out \
-L fwe,dout,tast,crate,parms,claus,nt,nd,te,truns,trun
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4e3b277f220fa70dcab21912c30f1d26d9bd8749
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62840
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch introduces useful macros (read/write/erase) and uses these
macros throughout the SPI operations.
Additionally, implicitly using the HSFC_CYCLE_READ macro for the SPI
read operation.
BUG=b:223630977
TEST=Able to perform read/write/erase operation on PCH 600 series
chipset (board name: Brya).
Additionally, no difference in flashrom binary seen while comparing
flashrom binary generated with CB:62888 and between CB:62888 to
CB:62868 below:
flashrom$ cmp flashrom flashrom_old
<<none>>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3ea74b668e5f8d8e4b3da2a8ad8b81f1813e1e80
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62868
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch introduces HSFC_FDBC_VAL(n) macro to use in SPI read and
write operations.
BUG=b:223630977
TEST=Able to perform read/write/erase operation on PCH 600 series
chipset (board name: Brya).
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie2512c85de9fc21286234b97f5842ecef1729787
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
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This patch introduces HSFC_FCYCLE_MASK(n) macro to cover both ICH and
PCH hardware sequencing FCYCLE Bit width.
BUG=b:223630977
TEST=Able to perform read/write/erase operation on PCH 600 series
chipset (board name: Brya).
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id222304165610c7ae48e365d72ec8fdeea51c51d
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
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This patch drops `_pprint_reg` macro as `pprint_reg` macro is
now able to call into msg_pdbg().
BUG=b:223630977
TEST=Able to display HSFS register offset properly as below
BIOS_CNTL = 0x8b: BIOS Lock Enable: enabled, BIOS Write Enable: enabled
Warning: Setting BIOS Control at 0xdc from 0x8b to 0x89 failed.
New value is 0x8b.
SPIBAR = 0x00007fce5a270000 (phys = 0xfe010000)
0x04: 0xf000 (HSFS)
HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=0, SCIP=0, FDOPSS=1, FDV=1,
FLOCKDN=1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iee7a23447de38423b61008b3242d28ce553ae0a2
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This patch uses `pprint_reg` macro instead `_pprint_reg` with explicit
register name and offset macros being passed as argument.
BUG=b:223630977
TEST=Able to display PCH100_HSFC.FCYCLE offset properly.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5a8d84639b7226bf82458a7310f306c5232cffe3
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch renames the `WET` macro definitions based on its
availability with PCH100 onwards chipset.
HSFC_WET_OFF -> PCH100_HSFC_WET_OFF
HSFC_WET -> PCH100_HSFC_WET
BUG=b:223630977
TEST=Able to perform read/write/erase operation on PCH 600 series
chipset (board name: Brya).
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id32cb4ccb83dd08e9b0b1ab30cc8e041dd059f5f
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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In light of `commit caa0335114a81`, extract out the get_param logic to
its own function to simplify the number of cleanup paths.
BUG=none
TEST=builds
Change-Id: I364febc05c870683cbad114583762b0c006f4bac
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63130
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configuration for W25Q64 was tested on hardware (W25Q64FV).
Emulation of W25Q128 in dummyflasher will be extended to support WP.
Haven't tested this one on hardware, but it's the same configuration as
for W25Q64 except that it has WPS.
W25Q64JV chip was renamed to W25Q64JV-.M (those with QPI).
W25Q64.V chip was split into W25Q64BV/W25Q64CV/W25Q64FV (no SR3 and WPS)
and W25Q64JV-.Q (SR3 and WPS, but no QPI).
Change-Id: Iccb69a8d3a0dd2192e2c938caddaf07b1889ed35
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Change-Id: I026c22ae1c22541d0024f164c827909ca4a34cf4
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/48380
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Because the enum is a different name to the one within cr50 it
was entirely unclear where these values were handled at the end-point
and what a untargetted REQ_ENABLE actually did. Comment to avoid
needing to chase this again.
BUG=b:224358254
TEST=builds
Change-Id: I8cc78a85660190c9f750bf67994f0d59d69592d8
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
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Drop not needed `-DCONFIG_BITBANG_SPI=1`
Change-Id: I2a519c929f7747af70568284823b51678751e285
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Makefile treats warnings as errors, so enable the same option
for meson.
Makefile has an option to disable "warnings as errors" option
from command line. The same can be achieved with meson, see
scenario 2 below.
TEST=I verified the following scenarious
1) check that warnings treated as errors by enforcing higher
warning level
`meson setup --warnlevel=3 --wipe`
`ninja test`
shows tons of errors because warning level 3 is pedantic,
build fails
2) disable "warning as errors" option from command line
`meson configure -Dwerror=false`
`ninja test`
Now all warnings are non-blocking for build, so tests pass
3) back home
`meson configure -Dwerror=true`
`meson setup --warnlevel=2 --wipe`
`ninja test`
No warnings and tests pass
4) defaults: create new directory and run meson will all default
options
No warnings, all tests pass.
Change-Id: I06c72abf1c861f9b35736e02ef7f4a4fb6909b97
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
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Makefile has optimisation level set explicitly. This patch
sets the same level s into meson build.
Also disable debug by default to correspond to make builds.
These two options (optimisation and debug) are linked together
in meson build, so they need to be set together to be properly
recognised for builds.
Alternative approach would be to use buildtype option (and do not
set optimisation and debug). However, none of the standard
buildtypes gives a combination that we need:
optimisation level s and debug disabled.
TEST=ninja test shows no warnings and tests pass
Change-Id: I4ca96a866529cac320e66516ef280d5100ceefab
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
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Makefile options were more restrictive and produced more
warnings. This patch adds missing warning options into
meson build.
Makefile also has -Wall and -Wextra specified explicitly,
however this is covered by warning_level=2 which is already
set in meson.build. warning_level info:
https://github.com/mesonbuild/meson/issues/3275
There are few warning options that are present in meson,
but not in Makefile. These are left as is.
TEST=ninja test shows no warnings and tests pass
Change-Id: Id401bfd642dc3c13d85bd9a2dba56ada38714c25
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
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Part 2 of fixing -Wmissing-prototypes warnings. This patch adds
headers with function prototypes and includes the headers into
source files. This fixes the warnings like this:
warning: no previous prototype for ‘function_name’
[-Wmissing-prototypes]
This patch is needed to sync compiler warning options between meson
and makefile.
TEST=running the following produces no warnings:
meson setup --wipe (to clean build directory)
ninja test
Change-Id: Ia1ff22deb2354569f277649c6575ef2d5ffbb6e0
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Part 1 of fixing -Wmissing-prototypes warnings. This patch is
adding static to all functions which are actually static.
This fixes the warnings like this:
warning: no previous prototype for ‘function_name’
[-Wmissing-prototypes]
This patch is needed to sync compiler warning options between meson
and makefile.
TEST=running the following produces no warnings:
meson setup --wipe (to clean build directory)
ninja test
Change-Id: Ic54da5ac1b2a46f55e3e3bee4ed952bdf59e8444
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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