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* chipset_enable: Mark Braswell as testedDavid Hendricks2017-08-191-1/+1
| | | | | | | | | | | | Reported by Uwe Vieweg: https://mail.coreboot.org/pipermail/flashrom/2017-August/015059.html Change-Id: Iaf7558af8737af36401f577ca7aba9fd7114a3df Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/20923 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Include <sys/types.h> wherever ssize_t is usedNico Huber2017-08-163-0/+3
| | | | | | | | | | | | `ssize_t` is a POSIX type (cf. IEEE Std 1003.1). Change-Id: I5f6f114523f541b3a8d845c6faee2c0b9f753bae Signed-off-by: Nico Huber <nico.h@gmx.de> Reported-by: Urja Rannikko <urjaman@gmail.com> Reviewed-on: https://review.coreboot.org/21015 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Urja Rannikko <urjaman@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ich_descriptors: Modify limits for C620/Lewisburg PCHDavid Hendricks2017-08-131-2/+3
| | | | | | | | | Change-Id: Ic8adc4b87993e65096166fa6d665432697070b4c Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/20936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
* rpci: Use pci_dev struct pointer to avoid API breaksYouness Alaoui2017-08-103-9/+25
| | | | | | | | | | | | | | | | | | | | | | The pci_dev structure is never meant to be used as is, but always as a pointer. By using the struct itself in undo_pci_write_data, we are risking data corruption, or buffer overflows if the structure size changes. This is especially apparent on my system where flashrom segfaults because I compile it with pciutils 3.3.0 and I run it on a system with pciutils 3.5.2. The struture size is different and causes a struct with the wrong size to be sent to the library, with invalid internal field values. This has been discovered and discussed in Change ID 18925 [1] [1] https://review.coreboot.org/#/c/18925/ Change-Id: Icde2e587992ba964d4ff92c33aa659850ba06298 Signed-off-by: Youness Alaoui <kakaroto@kakaroto.homelinux.net> Reviewed-on: https://review.coreboot.org/20784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ich_descriptors: Pretty print an assumed chipsetNico Huber2017-07-282-1/+19
| | | | | | | | | | | Change-Id: Id28cb3abc45c6e7f4c4accfc019579c7448c45d7 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20247 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* chipset_enable: Set 100 series chipsets to NTNico Huber2017-07-281-30/+30
| | | | | | | | | Change-Id: I9376a0c180b7e73751fbd3c8c37b693d358cbfb8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19047 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ich_descriptors: Update for Intel SkylakeNico Huber2017-07-283-159/+261
| | | | | | | | | | | | | | | | | | | | | | | Interpretation of component clocks changed. Also more regions and more masters are supported now. The number of regions (NR) is now static per chipset (10 in the 100 Series case) and not coded into the descriptor any more. v2: o Use guess_ich_chipset() for read_ich_descriptors_from_dump(). o Update region extraction in `ich_descriptors_tool`. TEST=Run `ich_descriptors_tool` over a 100 Series dump and checked that output looks sane. Run `ich_descriptors_tool` over dumps of five different older systems (1 x Sandy Bridge, 3 x Ivy Bridge, 1 x Haswell). Beside whitespace changes, regions not accounted by `NR` are not printed any more. Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18973 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ich_descriptors: Add function to guess chipset versionNico Huber2017-07-282-3/+66
| | | | | | | | | | | | | | | | | Add guess_ich_chipset() that takes fields from a descriptor dump and returns the lowest possible chipset version. Intel did several incompatible changes to the descriptor through the years. However, they forgot to add a version number. So we have to apply some heuristics to detect the chipset version in case of exter- nal flashing. Change-Id: Ie1736663dc33801b19d3e695c072c61a6c6345a2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20246 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ich_descriptors: Draw +0xfff into ICH_FREG_LIMIT()Nico Huber2017-07-284-9/+6
| | | | | | | | | | | The condition `base > limit` is still valid since `base` is always at least 4096 greater than `limit` in this case. Change-Id: I11ac0a50b3f32f47879e7cfb7a26068cd0572ede Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19046 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi: Add support for Intel SkylakeNico Huber2017-07-283-87/+233
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Sunrise Point PCH, paired with Skylake, has some minor changes in the HW sequencing interface: * Support for more flash regions moved PR* registers * Only 4KiB erase blocks are supported by the primary erase command * A second erase command for 64KiB pages was added * More commands were added for status register access etc. * A "Dedicated Lock Bits" register was added No support for the new commands was added. The SW sequencing interface seems to have moved register location and is not supported any more officially. It's also untested. Changes are loosely based on the Skylake support commit in Chromium OS by Ramya Vijaykumar: commit a9a64f9e4d52c39fcd3c5f7d7b88065baed189b1 Author: Ramya Vijaykumar <ramya.vijaykumar@intel.com> flashrom: Add Skylake platform support Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
* chipset_enable: Add support for Intel Skylake / KabylakeNico Huber2017-07-282-7/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All publicly known Skylake / Kabylake / Sunrise Point PCH variants share the same register interface [1..6]. Although all SPI configu- ration is now done through the SPI PCI device 1f.5, we can't probe for it directly since its PCI vendor and device IDs are usually hid- den. To work around the hidden IDs, we use another PCI accessor that doesn't rely on the OS seeing the PCI device. This handles SPI flashes only. While booting from LPC is still sup- ported, it seems nobody uses it any more. Some additional PCI IDs were gathered from driveridentifier.com. TEST=Compiled with B150 set to NT (instead of BAD) and checked for sane register readings. [1] 6th Generation Intel® Core(TM) Processor Families I/O Platform Datasheet - Volume 1 of 2 Revision 002EN Document Number 332995 [2] 6th Generation Intel® Processor I/O Datasheet for U/Y Platforms Volume 2 of 2 Revision 001EN Document Number 332996 [3] 7th Generation Intel® Processor Families I/O Platform Datasheet - Volume 1 of 2 Revision 002 Document Number 334658 [4] 7th Generation Intel® Processor Families I/O for U/Y Platforms Datasheet - Volume 2 of 2 Revision 002 Document Number 334659 [5] Intel® 100 Series and Intel® C230 Series Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 1 of 2 Revision 004EN Document Number 332690 [6] Intel® 100 Series Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 2 of 2 Revision 001EN Document Number 332691 Change-Id: I000819aff25fbe9764f33df85f040093b82cd948 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18925 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
* Drop redundant `enum msglevel`Nico Huber2017-07-136-45/+38
| | | | | | | | | | | | Use `enum flashrom_log_level` instead to avoid further confusion. Change-Id: I1895cb8f60da3abf70c9c2953f52414cd2cc10a9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20268 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Enable continuous SPI readsUrja Rannikko2017-07-132-35/+15
| | | | | | | | | | | | | Previous unnecessary page-by-page reading is repurposed to read by big naturally aligned areas (now chip size limited to 16MB for future-proofing of 4 byte addressed multi-die chips) and serprog hack for continuous reads is removed. Change-Id: Iadf909c9216578b1c5dacd4c4991bb436e32edc9 Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-on: https://review.coreboot.org/20223 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Remove djgpp-dos targetStefan Tauner2017-06-231-3/+0
| | | | | | | | | | It is not different to other x-compilations. Change-Id: Ia582b4cf622e670f1af439095ff58d62554232aa Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Reviewed-on: https://review.coreboot.org/20293 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Convert flashrom to gitStefan Tauner2017-06-2312-124/+405
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Drop support for Subversion in the getrevision script and Makefile. - Add .gitignore and .gitattributes file (the latter to limit exports). - Restore modification dates of the exported files from the SCM. - Stop exporting SCM log dumps to CHANGELOG. This makes no sense. - Do not export the pre-"compiled" manpage. It can be generated like anything else from the code dump when we export the respective variable. The latter is added with this change. - Add some initial client-side git hooks * When committing check for obvious stuff you never want anyway: - white space errors * When pushing to the upstream repository check mandatory rules: - existing signoffs and acks in all new commits - no deletions or creation of branches - do not rewrite history of the precious branches, even if forced NOTE: This patch is adapted from Stefan Tauner's original commit: https://mail.coreboot.org/pipermail/flashrom/2016-November/014877.html There are a few major differences: - This uses coreboot's commit-msg hook which includes support for generating and appending Change-Id. - djgpp-dos target removal is moved to a follow-up patch. - Version string changes are moved to a follow-up patch. Change-Id: I64eef21982cac0a0a7419bcd2c8a936672ae9cb2 Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/19206 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* udelay: Use clock_gettime() if available and preciseNico Huber2017-06-222-0/+78
| | | | | | | | | | | | | | | | | | | | | | | Instead of calibrating our busy loop against a coarse clock, check if a precise clock is available and loop against that. The former is unre- liable by definition on any modern system that may dynamically reclock the processor. v2: Apparently _POSIX_MONOTONIC_CLOCK being defined only means that the library knows about CLOCK_MONOTONIC. So check for its support at runtime and fall back to CLOCK_REALTIME if it's missing. TEST=Manually added a 10s loop and compared to real time. Run on Linux RPi3, Linux x86 and my original use case Linux in VirtualBox (Linux host). Change-Id: I85ad359823875237ada9cd027af3017d62e9a235 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19391 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Fix linking with libpayloadNico Huber2017-06-224-37/+36
| | | | | | | | | | | | | | | | o Move flashbuses_to_text() to flashrom.c, it's not a cli function. o Guard `!defined(HAVE_STRNLEN)`. This guard was introduced in 23e10b87 (Add a bunch of new/tested stuff and various small changes 24) to support older BSDs. It's probably completely broken because HAVE_STRNLEN is presumably a GNU autotools thing. But we can't fix it without retesting these older BSDs. Change-Id: I561135209b819361d125eeaeef9ff886d6bae987 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18738 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* fixup! Make read_ich_descriptors_from_dump() available in flashromNico Huber2017-06-201-0/+3
| | | | | | | | | | | | | Add a guard around read_ich_descriptors_via_fdo() which uses raw hardware access and is only called from `ichspi`. Fixes linking in case `NEED_RAW_ACCESS != 1`. Change-Id: I5a35c607df44cdbcbacb960f8922c1bf9f1f2002 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20265 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* fixup! Add a convenient libflashrom interfaceNico Huber2017-06-202-5/+6
| | | | | | | | | | | | Update `enum flashrom_log_level` to match `enum msglevel` again. They diverged already. Found by clang. Change-Id: Icf175c5f2a415365bd756ca813e724f6797459b2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* fixup! Add a convenient libflashrom interfaceNico Huber2017-06-202-2/+2
| | | | | | | | | | | | The buffer passed to flashrom_image_write() isn't `const`. It might be altered for full verification (with mixed contents if a layout is being used). Change-Id: Ibd8a9579e5dd859ae03b0deb3042b7035719e5de Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* ichspi: Drop `dev` parameter from init functionsNico Huber2017-06-203-8/+8
| | | | | | | | | | | | It's never used and has no clear contract (e.g. will the pointer stay valid beyond the call?). Change-Id: I0d4e7cc731364e86eff214b9022b842a577f9ef4 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Handle Intel Wildcat Point *LP* like Lynx Point LPNico Huber2017-06-203-9/+21
| | | | | | | | | | | | | | | | | | | | | | | The subtle difference was ignored when adding these chipsets. The integrated Wildcat Point LP PCH is documented in [1]. I'm not sure how to account for "Broadwell H" which seems not publicly documented. Maybe it's an unreleased HM9*, in which case the non-LP path should be correct. [1] Mobile 5th Generation Intel® Core(TM) Processor Family I/O, Intel® Core(TM) M Processor Family I/O, Mobile Intel® Pentium® Processor Family I/O, and Mobile Intel® Celeron® Processor Family I/O Datasheet Revision 004 Document Number: 330837 Change-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18883 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ich_descriptors: Fix more odd +1sNico Huber2017-06-201-9/+7
| | | | | | | | | | | | | | +1 on everything doesn't make software greater per se. v2: o Fix another +1. o Amend style of similar (not +1 suffering) code, too. Change-Id: Ifa5455c999e90ff9121aed29f542d71ac9ca2b1c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* fixup! Kill doit()Urja Rannikko2017-06-181-0/+2
| | | | | | | | | | | Fix building with CONFIG_INTERNAL=no because force_boardmismatch doesn't exist when internal is not enabled. Change-Id: Id9e715f09ef934bc36221b3e72c578ae96e0a3af Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-on: https://review.coreboot.org/20250 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Whitelist Roda/RV11 laptopNico Huber2017-06-141-0/+1
| | | | | | | | Change-Id: I036c1f8cb914c8e3cca9d17eb221b582d7414ae9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Add option to read ROM layout from IFDNico Huber2017-06-1411-25/+195
| | | | | | | | | | | | | | | | | | | | | | | | | Add an option --ifd to read the ROM layout from an Intel Firmware Descriptor (IFD). Works the same as the -l option, if given, -i specifies the images to update. v2: o Rebased on libflashrom, use libflashrom interface. o Use functions from ich_descriptors.c. v3: o Move ich_descriptors.o to LIB_OBJS, thus build it independent of arch and programmers. o Bail out if we aren't compiled for little endian. o Update flashrom.8.tmpl. v4: o Incorporated David's comments. o Removed single-character `-d` option. v5: Changed region names to match the output of `ifdtool --layout ...` Change-Id: Ifafff2bf6d5c5e62283416b3269723f81fdc0fa3 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Make read_ich_descriptors_from_dump() available in flashromNico Huber2017-06-143-27/+9
| | | | | | | | | | | | | | | | | I didn't really know what I was doing and hope removing the #ifdefs doesn't have negative side effects. The idea is to make the functions generally available for external flashing (e.g. you might want to flash an Intel machine using an ARM device as programmer). Beware of big endian trouble, I guess. :-P Change-Id: Ib3d38a622a581afee87b49777e775942cc901fc8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* cli_classic: Remove layout-for-write-only checkNico Huber2017-06-141-6/+0
| | | | | | | | Change-Id: I0f5e9623ca75bc4503aeb45ae346d7573c0fef2c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* cli_classic: Add option (-N, --noverify-all)Nico Huber2017-06-092-5/+26
| | | | | | | | | | | | | | This option specifies to verify included regions only after a write. It also reduces the data read before the write. v2: o Changed short option name to `-N`. o Added section in the manual page. Change-Id: I40b5983f56d62821d17b827b88b73d1d41a30bd7 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* flashchips: Add untested Winbond W25Q128.WNico Huber2017-06-052-1/+41
| | | | | | | | | | Only difference to its sibling W25Q128.V seems to be the supply voltage. Change-Id: I34ce7f1bdd0d2fb1b065031e5a689bb16ffc70db Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Kill doit()Nico Huber2017-06-034-418/+91
| | | | | | | | | | | | No words can describe this feeling. v2: Rejoice while removing more, orphaned code (layout.c). Change-Id: Id81177c50b4410e68dcf8ebab48386a94cd9b714 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Adapt CLI to use new libflashrom interface' print callbackNico Huber2017-06-034-8/+12
| | | | | | | | | | | | | | This renames CLI's print() to flashrom_print_cb() and registers it through the new libflashrom interface. v2: Add libflashrom.o to LIB_OBJS now that everything can be linked together. Change-Id: Idf19978eb8e340d258199193d2978f37409e9983 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Add Doxyfile for libflashrom documentationNico Huber2017-06-031-0/+2422
| | | | | | | | | | | | | | | Reference documentation for libflashrom can be build with doxygen. With doxygen Doxyfile documentation will be put into a libflashrom-doc/ subdirectory. v2: o Updated Doxyfile with `doxygen -u Doxyfile`. o Added flashrom.c to the INPUT list. Change-Id: I583bf9aa8c43049723aff498625d490c37832f13 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Add a convenient libflashrom interfaceNico Huber2017-06-035-7/+723
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a minimal libflashrom interface based on the draft in the wiki. While the glue code in libflashrom.c is build on top of the existing code instead on overhauling it, the interface in libflashrom.h is supposed to be stable. So we can keep the interface and adapt internals later if favoured, without breaking clients. A new make target, libinstall, is also added. It installs libflashrom.a and libflashrom.h in lib/ and include/ dirs respectively. Hooking this into the build would break linking of the CLI and is post- poned until that got fixed. v2: Rebase and fixes by Anton Kochkov. v3: o fl_image_*() rewritten with layout support (touch only included regions). o Moved read/erase/write/verify operations to flashrom.c. o Added layout pointer and flags to the flash context. v4: Removed libflashrom.o from LIB_OBJS until CLI is adapted. v5: o Incorporated David's comments. o Added `fl_flashprog_t` as dummy parameter to hide the fact that we have global state all around, and for future-proofness ofc. v6: o Change namespace prefix to flashrom_. o Remove typedefs. Change-Id: I00f169990830aa17b7dfae5eb74010d40c476181 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Add functions to read/erase/write/verify by layoutNico Huber2017-06-032-0/+352
| | | | | | | | | | | | | | | | | | | | | | | | | | Inspired by Lynxis' related work, this implements a foundation for layout based flash access. All operations iterate over the given layout regions. Erase and write then walk, per region, over all erase blocks in an inner loop (which might not be what we want, see note on optimization below). Special care has been taken that flash content is merged properly, in case an erase block is only partially covered by a layout region or even affects mul- tiple regions. A note on performance: In the case an erase block affects multiple regions, it will probably be read, erased and written for each region. Another approach would be to walk all erase blocks once and check for each erase block which regions it touches (i.e. for each erase block, merge data pontentially from the flash and all layout regions, then flash the combined data). That might result in cleaner code. I haven't tried it yet, though. Change-Id: Ic6194cea4c4c430e0cf9d586052508a865b09c86 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Give layouts their own typeNico Huber2017-06-033-50/+102
| | | | | | | | | | | | | | | | Introduce `struct flashrom_layout` and refactor layout.c a little, so we can reuse the layout from there and have other sources of layouts beside it. I didn't want to clutter up flash.h any more. So things went into a new layout.h. Change-Id: Icea1a58c283131cc9c5fde6f16d783538dc1a4c7 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
* ich_descriptors: Fix range checks for dumpsNico Huber2017-05-041-5/+5
| | | | | | | | | | These explicit off-by-one calculations were... off-by-one. Change-Id: If57c92ba28f91c4d72123ef0cfd2d9d5ac0a0656 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Remove undefined behaviorPatrick Georgi2017-05-042-6/+30
| | | | | | | | | | | | | | Per clang-3.9, the compiler fails on #define ...defined(...) statements as they're undefined behavior (apparently with different behavior between gcc/clang and msvc, too). See clang's cfe repo commit r258128 for details. Change-Id: I82b6235e11b425fae45eebbe06b08f81c5bdbb98 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/18792 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ich_descriptors_tool: Fix an off-by-oneNico Huber2017-04-261-1/+1
| | | | | | | | Change-Id: I008abd78c7c42bf3f17e68c192cd79dd427c5cb5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19045 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Move register decodes into enable_flash_ich_handle_gcs()Nico Huber2017-04-251-4/+18
| | | | | | | | | | | | | | | | | | GCS was decoded partly inside, partly outside this function. The decoding of `top_swap` was off, since passing a `uint8_t` as `bool` doesn't magically check bit0 only. While we are at it, rename this void function to enable_flash_ich_ report_gcs() as it's not doing anything. Beside debug output it doesn't have any side effects. Change-Id: I40addec98cb6840763adad30f9d0e27dadce6d1e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18882 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
* hwaccess: Constify `addr` argument of MMIO read functionsNico Huber2017-04-252-17/+17
| | | | | | | | | | Change-Id: I1419241a8332b74103b3921df2c615bdf91346a7 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18881 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* dediprog: Fix bug where too many transfers would be queuedNico Huber2017-04-201-1/+3
| | | | | | | | | | | | | We didn't check the total number of queued transfers in the inner most loop. Up to DEDIPROG_ASYNC_TRANSFERS - 1 invalid transfers could be queued therefore. So add another check on the total number. Change-Id: I91a8de47db7107455f5fc63ab2f13a0bd50c5b63 Signed-off-by: Nico Huber <nico.huber@secunet.com> Acked-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/19351 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
* dediprog: Reimplement target chip optionNico Huber2017-04-201-3/+14
| | | | | | | | | Change-Id: I594e2a6ee144260f8424d25b304f6ab41a9d3fad Signed-off-by: Nico Huber <nico.huber@secunet.com> Acked-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/19350 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
* Add iMac5,2 to board_enableArthur Heymans2017-04-161-0/+1
| | | | | | | | | | | | When running coreboot everything works, while on vendor bios it fails to erase anything until the 3th erase function of a SST25VF016B is tried. Change-Id: I5e4daaa67f98a47e237cd73962776da369c8f0b5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18943 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
* util: Add CH341a to z60_flashrom.rulesNico Huber2017-01-131-0/+3
| | | | | | | | Change-Id: I68b14ade3eb82598e4388735b8618d8c607ff494 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17596 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
* Make image parameter of cb_check_image constNico Huber2017-01-132-8/+8
| | | | | | | | | Change-Id: I811b3d6f1710154e055b03d5f27b1a8d9b3c0a43 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/17943 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* Increase flashrom version number to 0.9.9Stefan Tauner2016-03-131-1/+1
| | | | | | | | | Corresponding to flashrom svn r1954. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Urja Rannikko <urjaman@gmail.com>
* Fix fscanf format string security bug in layout.cCarl-Daniel Hailfinger2016-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | An internal security audit of the flashrom project by Carl-Daniel Hailfinger found a buffer overflow bug present in all flashrom versions since the year 2005. This bug was independently found and reported to flashrom.org by Cosmin Gorgovan a few days ago. A buffer on the stack and a buffer on the heap are affected by the overflow caused by an incorrect fscanf format string. The buffer overflow can only be triggered if the optional layout feature is used and if the user manually specifies a specially crafted layout file on the command line. Command line parsing and flash image handling do not trigger the buggy code path. Most usage of flashrom does not involve layout files. The fix in this commit (changed fscanf format string) can be applied to layout.c of all past flashrom versions. Corresponding to flashrom svn r1953. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Shutdown serial port in pony_spiCarl-Daniel Hailfinger2016-03-131-0/+17
| | | | | | | | | | Implement serial port shutdown both for regular termination and error conditions in pony_spi. Corresponding to flashrom svn r1952. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add a bunch of new/tested stuff and various small changes 25Stefan Tauner2016-03-139-75/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested mainboards: OK: - ASRock Fatal1ty 970 Performance and P4i65G Reported by anonymous email message ID: 932677687262b1300eaf14260999d9262c31@guerrillamail.com The latter actually had a tested board enable already. Flash chips: - Eon EN25Q128 to PREW (+PREW) Reported by Adrian Graham - GigaDevice GD25VQ41B to PREW (+PREW) Reported by David Hendricks - Winbond W39V040FB to PREW (+EW) Reported by fjed on IRC Miscellaneous: - Change PCI IDs of "MS-6577 (Xenon)" board enable. The previous IDs contained the on-board display adapter which is disabled when a dedicated graphics card is installed. - Add a note to the README how to overcome the clang warning if only a single programmer is enabled. - Fix some typo and manpage problems found by lintian - r1920 introduced some explicit calls to pkg-config instead of $(PKG_CONFIG). This patch corrects that. - Make MS-7094 (K8T Neo2-F V2.0) board enable less contestable. Previous PCI IDs were board-specific but ot the other of devices that could be disabled by the firmware or that vary among hardware revions. There are no good alternatives available. However, since we always have a DMI decoder available now, we can use non-board-specific devices without taking risks. Thanks to Uwe Hermann for reporting and testing. - Some other small changes to clean up whitespace and fix some warnings from Debian's lintian. Corresponding to flashrom svn r1951. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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