| Commit message (Collapse) | Author | Age | Files | Lines |
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Add an optional sub-parameter to the -i parameter to allow building the
image to be written from multiple files. This will also allow regions to
be read from flash and written to separate image files.
This is a rebase of a patch that was ported from chromiumos. A lot of
things have changed, but the idea is the same.
Original patch by Louis Yung-Chieh Lo <yjlou@chromium.org>:
Summary: Support -i partition:file feature for both read and write.
Commit: 9c7525f
Review URL: http://codereview.chromium.org/6611015
Ported version by Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
and Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>:
Summary: [PATCH 2/6] layout: Add -i <region>[:<file>] support.
Review URL: https://mail.coreboot.org/pipermail/flashrom/2013-October/011729.html
Change-Id: Ic5465659605d8431d931053967b40290195cfd99
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Signed-off-by: Daniel Campello <campello@chromium.org>
Co-Authored-by: Edward O'Callaghan <quasisec@google.com>
Co-Authored-by: Daniel Campello <campello@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/23021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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The change makes it possible to mock functions from hwaccess_x86_io.h
in tests by replacing this header with a different one when built
for a test environment. The rest of hwaccess.h is fine and works
for the test environment.
BUG=b:181803212
TEST=make clean && make CONFIG_EVERYTHING=yes VERSION=none
Build flashrom before and after this patch, flashrom binary
is the same (diff flashrom_before flashrom_after shows no diffs)
Change-Id: Idd04c7b36b24e9da339348a015df4f43a03744f7
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The current implementation tests a particular path of the init
procedure. There are two ways for it to succeed: reading the buffer
size from sysfs and the fallback to getpagesize(). This test does
the latter (fallback to getpagesize).
Extract from meson-logs/testlog.txt for new test:
[ RUN ] linux_spi_init_and_shutdown_test_success
Testing programmer_init for programmer=25 ...
__wrap_open64 is called
__wrap_ioctl is called
__wrap_ioctl is called
__wrap_ioctl is called
__wrap_fopen64 is called
... programmer_init for programmer=25 successful
Testing programmer_shutdown for programmer=25 ...
... programmer_shutdown for programmer=25 successful
[ OK ] linux_spi_init_and_shutdown_test_success
BUG=b:181803212
TEST=builds and ninja test
Change-Id: I4911fbb6f04371283f0e62d2196bdd691a227584
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52498
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Introduce test to exercise that init and shutdown of drivers
correctly manage the drivers life-time state. We constrain
ourselves to dummyflasher in particular here as it does not need
any mocking.
BUG=b:181803212
TEST=builds and ninja test
Change-Id: I3c0ef73397f00c1db7aabb5f9f00cb43525af29c
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Calls to __wrap functions are now logged to stdout, makes
it easier to understand what’s happening, really helps
when writing tests (and can be useful when debugging tests).
TEST=builds and ninja test
BUG=b:181803212
Change-Id: Ifcef55c9cdb7756c38dcc44fdc57cd88c3d65e70
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52496
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Shutdown function was covering two different jobs here: 1) the actual
shutdown which is run at the end of the driver's lifecycle and
2) cleanup in cases when initialisation failed. Now, shutdown is only
doing its main job (#1), and the driver itself is doing cleanup
when init fails (#2).
The good thing is that now resources are released/closed immediately
in cases when init fails (vs shutdown function which was run at some
point later), and the driver leaves clean space after itself if init
fails.
And very importantly this unlocks API change which plans to move
register_shutdown inside register master API, see
https://review.coreboot.org/c/flashrom/+/51761
TEST=builds and ninja test from 51487
BUG=b:185191942
Change-Id: I6d62d43dd8b6ebc595f9fd747e0f4cd80f3c10da
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Label mec1308_init_exit now serves as failed init path, it does
cleanup and returns 1, so it is renamed into init_err_exit.
Since all error paths return 1, and successful init is separated
from failure, there is no need to have ret variable anymore.
TEST=builds and ninja test from 51487
BUG=b:185191942
Change-Id: Ibf35335501e59636c544af124ad7a04a186790b4
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This allows char *p to become a local variable in check_params,
and it is allocated and freed within check_params function.
Which means init function does not need char *p anymore,
in particular does not need to free it - and this makes cleanup
after failed init easier.
As a good side effect, init function becomes easier to read.
TEST=builds and ninja test from 51487
BUG=b:185191942
Change-Id: If5be7709e93233a2e7ea9133de50382d2524a55f
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Since jaylink context and jaylink device handle are not global
variables anymore, but members of the struct jlink_spi_data,
jaylink_ prefix can be dropped from members names and moved to
struct variable name. Follow up on 52560.
BUG=b:185191942
TEST=builds
Change-Id: If6e68e0dabb6bfad1088ff975445961294bbc03d
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Miklós Márton <martonmiklosqdev@gmail.com>
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The device ID for H310C can be found in Intel document 335192-004, but
the device ID for B365 is not there. Other sites list these IDs:
https://linux-hardware.org/index.php?id=pci:8086-a2ca-1462-7c09 (H310C)
https://linux-hardware.org/index.php?id=pci:8086-a2cc-1849-a2cc (B365)
Both of these PCHs have been tested as well.
Change-Id: If9f0a49a0f1821e5592213e07962ee48654cdc07
Tested-by: Timofey Komarov <happycorsair@yandex.ru>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52605
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds CMP-H support. They are HM470, WM490, QM480,
W480, H470, Z490 and Q470.
TEST=build flashrom and run on CML-S with CMP-H
flashrom -p internal -w ./coreboot.rom
reboot and check the code is flashed correctly
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: Ic7f04fc5cbe3422cbd219c46586c32fc847c921f
Reviewed-on: https://review.coreboot.org/c/flashrom/+/37677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Only mattering difference to the MX25L3273E seems to be the voltage
range (starting at 2.65V instead of 2.7V). I don't think that would
justify yet another entry.
Change-Id: I73402dddedf360ab84caed4c019efe27b477d4c2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52570
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The datasheet says 4K bits, maybe just a copy-paste error.
Change-Id: I42b10aa09c969e5c5e7102b1e8ab496f52bd27bb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Read tested on CH341A
Change-Id: I25b776204affda94cc7e753e7671ef9d3d9508f1
Signed-off-by: Christian Kudera <coreboot@kudera.at>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Looks like BoHong Microelectronics has the same vendor ID and makes very
similar chips. For instance, Boya BY25Q128AS and BoHong BH25Q128AS have
the same specifications and their datasheets are mostly identical.
Change-Id: I8d6951797daeeecca6af200c995297c0394adefd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52550
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This was missed because `uint32_t` is `unsigned int` in most cases.
However, it is not the case for DJGPP 6.1.0 for some reason.
Tested with manibuilder, solves some build errors on the DJGPP target.
Change-Id: I656a72b85d4c70b57f6ff9268186a4a60933f8a9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52473
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested on MacBook Air 4,2.
Change-Id: Ia31c9d336d6ffe441323616174018b0f6a8897bd
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/51320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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In previous patches 52283, 52284, 52285 there were some unresolved
comments left, resolving [and replying to] all of that here.
TEST=builds and ninja test from 51487
BUG=b:185191942
Change-Id: I27a718b515fc474f63b3e61be58a6f9302527559
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Looks like these build fine. Add all the 9.1 targets to
the default run.
Change-Id: Ic323ced43132921d9f6f2c0d5fcf9c581afec0c7
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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It turned out that the `--memory-size` given at install time is
not persistent. All later anita runs use an arch-dependent default
(32M for i386, so this might explain why it was never stable).
Assuming most machines have >1GiB RAM per processor core available,
we can also increase the runtime size further (better to waste some
RAM than to wait very long because it starts swapping things out).
We choose 512MiB for 64-bit targets and 256MiB for 32-bit ones.
However, we don't need that much for the initial installation step
and it also decides the size of the swap partition. So we use a
smaller size initially that's just enough to get us through the
installation quickly enough (192MiB & 128MiB).
Change-Id: I255c41aeb92cda29ed23a236017472982e839530
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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There is no disk label `a` on non-x86 (at least not on Sparc64).
Instead, we use the whole disk which is `d` on x86 and `c` else-
where. `newfs` and `fsck` needs a little help in this scenario.
Change-Id: Ib298d9cbf5d49ff38a898f4ce3ad54bb6af98d86
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The anita-based NetBSD targets need noisy, per-target handling.
Factor it out into another Makefile.
Change-Id: I0a3ca751b42f1ca8c05d93eb9740bb0ee5cc6d09
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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emu_data *data is allocated in init function and needs
to be freed in shutdown function.
BUG=b:181803212
TEST=builds and ninja test
Change-Id: I36f76d84d3547d081c64857e06da23ee63cc5594
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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This reverts commit 5e5c3f15efe262ff23642dd543faf6a9dbb3bbdb.
Reason for revert: Breaks building on PowerPC, NetBSD, DJGPP, and it is
possible that SPARC fails to build as well.
Change-Id: I57b5125207de3fd156dface67cba605da893d6aa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Move global singleton states into a struct and store within
the spi_master data field for the life-time of the driver.
This is one of the steps on the way to move spi_master data
memory management behind the initialisation API, for more
context see other patches under the same topic "register_master_api".
TEST=builds
BUG=b:185191942
Change-Id: If13ad0c979ccf62ca4ccbd479d471c657895ef59
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Miklós Márton <martonmiklosqdev@gmail.com>
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DOS (DJGPP 6.1.0) has no USB support.
Change-Id: I36ee1edfb0e5b8d4e2b099c0f7f8aac64ed7884f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I726006fe2c1780361bdf6f9a1ddd84da0733642d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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his ---> this
Change-Id: Ibcc04a1581b3ba0dcd86e6f900c146823ebcd84a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Once upon a time flashrom had a entry point function called
doit(). Excise the last mention of it here so that we may
never mention it again.
BUG=none
TEST=none
Change-Id: I40d815b7154456c323b4230cd3fed2cc2e8e3641
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This fixes building with musl libc on alpine:i386-v3.7.
Change-Id: Ibd478f3fcd6b6803098035dbdc47f72f6ab3fa6b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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A bit more details: since register_shutdown has moved a few lines
below, now ene_enter_flash_mode is called before the shutdown function
is registered. ene_enter_flash_mode can fail (at least in theory,
it has some return 1s), but its return value is not analyzed, so even if
it returns non-0, execution goes further and register_shutdown will
happen anyway.
It is a separate question whether the return value of
ene_enter_flash_mode needs to be analyzed or is it ok to ignore it,
but in this patch I plan to keep the same behaviour, and probably I
will get back to error handling later.
This unlocks API change which plans to move register_shutdown inside
register master API, see https://review.coreboot.org/c/flashrom/+/51761
TEST=builds
BUG=b:185191942
Change-Id: If89a758c91c77486adbac2779449bcd71ab8fc78
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Given that the buffer size is known in advance, using malloc() is not
necessary. To avoid open-coding buffer sizes, add some trailing null
characters to `I2C_DEV_PREFIX`, as placeholders for bus number digits.
Finally, replace the now-unnecessary `goto` statements with `return`.
Change-Id: I6060749c6ded10949344caee3cc3943306e74a1c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Reflow long lines, drop unnecessary parentheses, add spaces after `if`
and `while` keywords and add braces to a single-statement `else if`
block that follows a multi-statement `if` block.
TEST=Build with `make distclean && make VERSION=none -j` with and
without this patch, the flashrom executable does not change.
Change-Id: Iaa5277b12fca192c46c11f5e0f375dc43d06bf5c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Fix a few typos and a copy-paste error in log messages.
Change-Id: Ic69503f60a59aa0f4b991eaa2a7be40a7d9c1301
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Miklós Márton <martonmiklosqdev@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Move global singleton states into a struct and store within
the spi_master data field for the life-time of the driver.
This is one of the steps on the way to move spi_master data
memory management behind the initialisation API, for more
context see other patches under the same topic "register_master_api".
TEST=builds
BUG=b:140394053
Change-Id: I93408c2ca846fca6a1c7eda7180862c51bd48078
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Shutdown function was covering two different jobs here:
1) the actual shutdown which is run at the end of the driver's
lifecycle and 2) cleanup in cases when initialisation failed.
Now, shutdown is only doing its main job (#1), and the driver
itself is doing cleanup when init fails (#2).
The good thing is that now resources are released/closed immediately
in cases when init fails (vs shutdown function which was run at some
point later), and the driver leaves clean space after itself if init fails.
And very importantly this unlocks API change which plans to move
register_shutdown inside register master API, see this
https://review.coreboot.org/c/flashrom/+/51761
TEST=builds
BUG=b:140394053
Change-Id: I1c8da2878cd0e85a1e43ba9b4b8e6f3d9f38ae5c
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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To get max_kernel_buf_size is a piece of logic on its own, it opens
resources and closes resources, also has some local variables only
for this task. Extracting get_max_kernel_buf_size() as a separate
function simplifies init flow and allows to remove global state from linux_spi
(see next patches in this chain).
TEST=builds
BUG=b:140394053
Change-Id: I4b8c5775fb8f4b0dff702fcc0fb258221254c659
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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While it's not posixly-correct, it's possible that a user, script, or
application may attempt to start flashrom with stdout or stderr
closed. It's possible that we'll get a file descriptor of 1 or 2 when
opening a flash device (such as Linux MTD), and flashrom will send
garbage debug logs to the flash:
# bash -c "exec >&- flashrom ..."
Observed corruption:
43 40 45 42 45 44 00 00 00 00 00 00 01 00 00 00 |C@EBED..........|
00 02 00 00 63 65 73 73 66 75 6c 6c 79 0a 46 6f |....cessfully.Fo|
75 6e 64 20 50 72 6f 67 72 61 6d 6d 65 72 20 66 |und Programmer f|
6c 61 73 68 20 63 68 69 70 20 22 4f 70 61 71 75 |lash chip "Opaqu|
65 20 66 6c 61 73 68 20 63 68 69 70 22 20 28 38 |e flash chip" (8|
31 39 32 20 6b 42 2c 20 50 72 6f 67 72 61 6d 6d |192 kB, Programm|
65 72 2d 73 70 65 63 69 66 69 63 29 20 6d 61 70 |er-specific) map|
70 65 64 20 61 74 20 70 68 79 73 69 63 61 6c 20 |ped at physical |
61 64 64 72 65 73 73 20 30 78 30 30 30 30 30 30 |address 0x000000|
30 30 2e 0a ff ff ff ff ff ff ff ff ff ff ff ff |00..............|
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
...
While for most applications, closing stdout or stderr would just lead
to obsure bugs, for flashrom, we should have extra safety guards, as
this could mean that we might be bricking a device instead.
Add a basic safety check.
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I751c9dd88ad1d30283b94bd2185b4f8f25569c8f
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Shutdown function was covering two different jobs here:
1) the actual shutdown which is run at the end of the driver's
lifecycle and 2) cleanup in cases when initialisation failed.
Now, shutdown is only doing its main job (#1), and the driver
itself is doing cleanup when init fails (#2).
The good thing is that now resources are released/closed immediately
in cases when init fails (vs shutdown function which was run at some
point later), and the driver leaves clean space after itself
if init fails.
And very importantly this unlocks API change which plans to move
register_shutdown inside register master API, see this
https://review.coreboot.org/c/flashrom/+/51761
TEST=builds
BUG=b:185191942
Change-Id: I71f64ed38154af670d4d28b8c7914d87fbc75679
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Move global singleton states into a struct and store within
the spi_master data field for the life-time of the driver.
This is one of the steps on the way to move spi_master data
memory management behind the initialisation API, for more
context see other patches under the same topic "register_master_api".
TEST=builds
BUG=b:140394053
Change-Id: I67518a58b4f35e0edaf06ac09c9374bdf06db0df
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Change-Id: I04a0fdf9b5126b9f4006e8229c3926ceb1013456
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/51979
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I3897b8d980425ecbb89b238d4a766f628cf9d3e6
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/51978
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change removes the build dependency on libpci for config_rayer_spi
it also makes sure that dependency on raw_access is maintained.
Signed-off-by: Daniel Campello <campello@chromium.org>
Change-Id: If7206a69d031c9bba9475a9e6769f6ef35701379
Reviewed-on: https://review.coreboot.org/c/flashrom/+/51929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The Raiden debug external spi programmer need only depend
on libusb and is unrelated to libpci. Correct meson and gnu make
builds where meson had configuration in the incorrect section
and gnu make artifactually disabled the build on Windows/MinGW
which doesn't have libpci.
BUG=none
TEST=still continues to build.
Change-Id: I2d6a8c33a2228abf006a9b278bcb7133765c7074
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/51930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This commit enables the feature and makes changes to existing
files and tests. I am writing more new tests with this.
Commit includes tests/flashrom.c because after enabling memory
checks the test started to fail (it used to leak memory indeed).
If you are wondering how to verify it works (because at the moment
all tests [still] pass so it’s not obvious that anything has
changed), then for example:
1) Remove free’s in flashbuses_to_text_test_success test, and it
will fail with message similar to this (line numbers from your local
source)
[ ERROR ] --- Blocks allocated...
../flashrom.c:1239: note: block 0x55f42304b640 allocated here
../flashrom.c:1239: note: block 0x55f42304b5c0 allocated here
../flashrom.c:1239: note: block 0x55f42304b3d0 allocated here
../flashrom.c:1239: note: block 0x55f42304b700 allocated here
../flashrom.c:1239: note: block 0x55f42304b780 allocated here
../flashrom.c:1239: note: block 0x55f42304bb00 allocated here
../flashrom.c:1239: note: block 0x55f42304b810 allocated here
ERROR: flashbuses_to_text_test_success leaked 7 block(s)
2) Add char *temp = malloc just before return from strcat_realloc
[ ERROR ] --- Blocks allocated...
../helpers.c:88: note: block 0x55a51307b6c0 allocated here
../helpers.c:88: note: block 0x55a51307b9e0 allocated here
ERROR: strcat_realloc_test_success leaked 2 block(s)
BUG=b:181803212
TEST=builds and ninja test
nm builddir/tests/flashrom_unit_tests.p/.._flashrom.c.o
nm builddir/tests/flashrom_unit_tests.p/flashrom.c.o
nm builddir/flashrom.p/flashrom.c.o
Change-Id: I0c6b6b8dc17aaee28640e3fca3d1fc9f7feabf5f
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/51243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Reorder functions to avoid forward-declarations of structs. Similar
thing was done earlier for functions declarations, this patch takes
care of structs declarations.
BUG=b:140394053
TEST=builds
objdump -d is identical
objdump -s only difference is version number
Change-Id: I256bd7c763efc010fc1f29f7c5853f150ac10739
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/51731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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The chip was marked as TESTED_OK_PREW in the cros tree by
`commit 419e32ae457cc36b03757b89471a7ce3770e9611`.
Quoting from the original commit message:
> TEST=Tested writes using Servo
Change-Id: Id7f44a41d6b2c397f1ce2e345f8ab44e95e4cfa2
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/51736
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested read/write/erase/verify with FT232H programmer.
Change-Id: Ia7d52b69eb571113fe3c60ec9a139ee67180509b
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/51735
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The chip was marked as TESTED_OK_PREW in the cros tree by
`commit b2f900273aac329b82089e4dbc5a8ba3d032fff0`.
Quoting from the original commit message:
> TEST=read and write BIOS on glimmer with Eon device.
Change-Id: I13dc3e6bde9e4581fdd5856a412918784b913fbc
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/51734
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I68d3055d0d6b80b79673f66769663387fe15dcde
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/51518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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